Abstract: A reconfigurable processor invoking data stream pipelining is configured to associate a restore buffer with each incoming data stream. The buffer is configured to be of sufficient size to maintain data values dispatched to a loop so as to restore values fetched and lost due to loop overshoots. The restore buffer stores the values that were recently fetched from the buffer to the loop. To determine how many data values should be restored, the loop counts the number of the data values it takes from each data stream and the number of valid loop iterations that take place. Once a loop termination is detected, the loop halts the fetching of values from the restore buffer and compares, for each stream, the number of loop iterations with the number of values fetched. The difference is the number of extra values that were taken from the restore buffer and are restored.

Abstract: Disclosed herein are mobile electronic devices utilizing reconfigurable processing techniques to enable higher speed applications with lowered power consumption for, inter alia, increased device battery life. The techniques disclosed herein enable greatly enhanced compression/decompression as well as encryption and decryption functionality to be provided in addition to overall greater processing capability particularly in those applications wherein minimization of power consumption is desired. Package-on-package and other assembly techniques may be used to provide the reconfigurable processor in a small footprint package.

Abstract: A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation.

Abstract: A reconfigurable processor invoking data stream pipelining is configured to associate a restore buffer with each incoming data stream. The buffer is configured to be of sufficient size to maintain data values dispatched to a loop so as to restore values fetched and lost due to loop overshoots. The restore buffer stores the values that were recently fetched from the buffer to the loop. To determine how many data values should be restored, the loop counts the number of the data values it takes from each data stream and the number of valid loop iterations that take place. Once a loop termination is detected, the loop halts the fetching of values from the restore buffer and compares, for each stream, the number of loop iterations with the number of values fetched. The difference is the number of extra values that were taken from the restore buffer and are restored.

Abstract: An embodiment of the invention includes a method of forming a control-dataflow graph that includes separating a control flow graph into two or more basic blocks, and converting said two or more basic blocks into code blocks, where the code blocks are formed into the control-dataflow graph. Another embodiment of the invention includes a method of forming a control-dataflow graph that includes separating a control flow graph into two or more basic blocks, forming a lode node in at least one of said basic blocks, forming a store node in at least one of said code blocks, inserting a delay node in at least one of said code blocks, segregating external hardware logic modules from said control flow graph, and converting said two or more basic blocks into code blocks, wherein the code blocks are formed into the control-dataflow graph.

Abstract: An embodiment of the invention includes a method of simulating a hybrid instruction processor and reconfigurable processor implemented algorithm which utilizes a runtime selectable emulation library that emulates a reconfigurable processor and its resources, and a control-data flow emulator that emulates the reconfigurable logic for the algorithm. Another embodiment of the invention includes a method of simulating a control-dataflow graph that includes building an internal representation of the control-dataflow graph that includes one or more dataflow code blocks, and simulating the control-dataflow graph as a sequence of code block dataflow executions, where control is passed from one code block to another code block based on the output value of the code block until EXIT is reached.

Abstract: A reconfigurable processor that includes a computational unit and a data prefetch unit coupled to the computational unit, where the data prefetch unit retrieves data from a memory and supplies the data to the computational unit through memory and a data access unit, and where the data prefetch unit, memory, and data access unit is configured by a program. Also, a reconfigurable hardware system that includes a common memory; and one or more reconfigurable processors coupled to the common memory, where at least one of the reconfigurable processors includes a data prefetch unit to read and write data between the unit and the common memory, and where the data prefetch unit is configured by a program executed on the system. In addition, a method of transferring data that includes transferring data between a memory and a data prefetch unit in a reconfigurable processor; and transferring the data between a computational unit and the data prefetch unit.

Abstract: A control-flow dataflow graph pipelined loop structure that includes a loop body that processes an input value to generate an output value in successive iterations of the loop body, where the output value is captured by a circulate node coupled to the loop body, a loop valid node coupled to the loop body that determines a final loop iteration, and an output value storage node coupled to the circulate node, where the output value storage node ignores output values generated after the loop valid node determines the final loop iteration has occurred. Also, a control-flow dataflow graph pipelined loop structure that includes a loop body that processes an input value to generate an output value in successive iterations of the loop body, where the output value is captured by a circulate node coupled to the loop body, and a loop driver node coupled to the circulate node, where the loop driver node sets a period for each iteration of the loop body.

Abstract: A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation.

Abstract: A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation.

Abstract: An embodiment of the invention includes a system for partitioning a control-flow graph representation into a reconfigurable portion and an instruction processor portion. Another embodiment of the invention includes a method of partitioning a control-dataflow graph representation that includes dividing the control-dataflow graph into two or more partition blocks, comparing the estimated performance of at least one of the partition blocks as reconfigurable logic versus instruction processor code; and assigning said at least one of the partition blocks to reconfigurable hardware or an instruction processor based on said comparing step.

Abstract: The present invention includes a method of computing a function array in reconfigurable hardware that includes forming in the reconfigurable hardware a first delay queue and a second delay queue, inputting from a source array outside the reconfigurable hardware a first value into the first delay queue and a second value into the second delay queue, defining in the reconfigurable hardware a window array comprising a first cell and a second cell, inputting the first value from the first delay queue into the first cell and the second value from the second delay queue into the second cell, and calculating an output value for the function array based on the window array. The present invention also includes a method of loop stripmining and a method of calculating output values in a fused producer/consumer loop structure.

Abstract: A reconfigurable processor that includes a computational unit and a data prefetch unit coupled to the computational unit, where the data prefetch unit retrieves data from a memory and supplies the data to the computational unit through memory and a data access unit, and where the data prefetch unit, memory, and data access unit is configured by a program. Also, a reconfigurable hardware system that includes a common memory; and one or more reconfigurable processors coupled to the common memory, where at least one of the reconfigurable processors includes a data prefetch unit to read and write data between the unit and the common memory, and where the data prefetch unit is configured by a program executed on the system. In addition, a method of transferring data that includes transferring data between a memory and a data prefetch unit in a reconfigurable processor; and transferring the data between a computational unit and the data prefetch unit.

Abstract: The present invention includes a method of computing a function array in reconfigurable hardware that includes forming in the reconfigurable hardware a first delay queue and a second delay queue, inputting from a source array outside the reconfigurable hardware a first value into the first delay queue and a second value into the second delay queue, defining in the reconfigurable hardware a window array comprising a first cell and a second cell, inputting the first value from the first delay queue into the first cell and the second value from the second delay queue into the second cell, and calculating an output value for the function array based on the window array. The present invention also includes a method of loop stripmining and a method of calculating output values in a fused producer/consumer loop structure.

Abstract: An embodiment of the invention includes a method of simulating a hybrid instruction processor and reconfigurable processor implemented algorithm which utilizes a runtime selectable emulation library that emulates a reconfigurable processor and its resources, and a control-data flow emulator that emulates the reconfigurable logic for the algorithm. Another embodiment of the invention includes a method of simulating a control-dataflow graph that includes building an internal representation of the control-dataflow graph that includes one or more dataflow code blocks, and simulating the control-dataflow graph as a sequence of code block dataflow executions, where control is passed from one code block to another code block based on the output value of the code block until EXIT is reached.

Abstract: An embodiment of the invention includes a system for partitioning a control-flow graph representation into a reconfigurable portion and an instruction processor portion. Another embodiment of the invention includes a method of partitioning a control-dataflow graph representation that includes dividing the control-dataflow graph into twp or more partition blocks, comparing the estimated performance of at least one of the partition blocks as reconfigurable logic versus instruction processor code; and assigning said at least one of the partition blocks to reconfigurable hardware or an instruction processor based on said comparing step.

Abstract: A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation.

Abstract: A control-flow dataflow graph pipelined loop structure that includes a loop body that processes an input value to generate an output value in successive iterations of the loop body, where the output value is captured by a circulate node coupled to the loop body, a loop valid node coupled to the loop body that determines a final loop iteration, and an output value storage node coupled to the circulate node, where the output value storage node ignores output values generated after the loop valid node determines the final loop iteration has occurred. Also, a control-flow dataflow graph pipelined loop structure that includes a loop body that processes an input value to generate an output value in successive iterations of the loop body, where the output value is captured by a circulate node coupled to the loop body, and a loop driver node coupled to the circulate node, where the loop driver node sets a period for each iteration of the loop body.

Abstract: An embodiment of the invention includes a method of forming a control-dataflow graph that includes separating a control flow graph into two or more basic blocks, and converting said two or more basic blocks into code blocks, where the code blocks are formed into the control-dataflow graph. Another embodiment of the invention includes a method of forming a control-dataflow graph that includes separating a control flow graph into two or more basic blocks, forming a lode node in at least one of said basic blocks, forming a store node in at least one of said code blocks, inserting a delay node in at least one of said code blocks, segregating external hardware logic modules from said control flow graph, and converting said two or more basic blocks into code blocks, wherein the code blocks are formed into the control-dataflow graph.