Abstract: In an embodiment, a camera sensor module is communicatively coupled to a vision processing system. The camera sensor module captures a plurality of exposures, produces an HDR-combined stream, and sends both the HDR-combined stream and the plurality of exposures to the vision processing system. A first ISP of the vision processing system performs color processing to produce a color-processed HDR-combined stream for neural network processing, presentation to a human, and/or computer vision processing. At least one other ISP of the vision processing system performs color processing to collect exposure-specific statistics on at least one of the plurality of exposures for determining camera calibration data for the camera sensor module.

Abstract: Examples disclosed herein provide mechanisms for controlling a sensor in a multiple System on Chip (SoC) environment that allows one of the multiple System on Chips to be selected as a host System on Chip. The host System on Chip may lock the sensor to apply setting updates only from the host System on Chip that has locked the sensor. This lock may be broadcast to all sensors over an embedded data channel sent to all System on Chips receiving the sensor data. In addition, a safety monitor may be included to detect if the host System on Chip is functioning properly so that another System on Chip may be selected as a new host System on Chip.

Abstract: Examples disclosed herein provide mechanisms for controlling a sensor in a multiple System on Chip (SoC) environment that allows one of the multiple System on Chips to be selected as a host System on Chip. The host System on Chip may lock the sensor to apply setting updates only from the host System on Chip that has locked the sensor. This lock may be broadcast to all sensors over an embedded data channel sent to all System on Chips receiving the sensor data. In addition, a safety monitor may be included to detect if the host System on Chip is functioning properly so that another System on Chip may be selected as a new host System on Chip.

Abstract: In an embodiment, a camera sensor module is communicatively coupled to a vision processing system. The camera sensor module captures a plurality of exposures, produces an HDR-combined stream, and sends both the HDR-combined stream and the plurality of exposures to the vision processing system. A first ISP of the vision processing system performs color processing to produce a color-processed HDR-combined stream for neural network processing, presentation to a human, and/or computer vision processing. At least one other ISP of the vision processing system performs color processing to collect exposure-specific statistics on at least one of the plurality of exposures for determining camera calibration data for the camera sensor module.

Abstract: Methods and apparatus to manage image signal processor (ISP) data traffic is provided. The apparatus includes an ISP having an ISP front-end configured to receive image data and a first memory configured to store the image data. The ISP front-end is further configured to output the image data stored in the first memory to a second memory via a memory link in response to the image data stored in the first memory reaching a size threshold. Another apparatus includes apparatus includes a camera sensor configured to output image data in a camera mode, an ISP on a die, a camera link coupling the camera sensor and the ISP, a memory, and a memory link coupling the ISP and the memory. The memory link is configured to enter a low-power mode in the camera mode.

Abstract: Alternative display options for vehicle telltales are disclosed. In one aspect, a fault condition in a telltale is detected, and the telltale is presented through a secondary display system in the vehicle, potentially bypassing any local control unit for the secondary display system. For example, a video telltale may be presented on an infotainment display after detection of a fault in the original telltale. By presenting the telltale in an alternate display, the operator remains informed of sensor conditions in the automobile and may take remedial action to fix the fault as well as any conditions which trigger a telltale.

Abstract: Methods and apparatus to manage image signal processor (ISP) data traffic is provided. The apparatus includes an ISP having an ISP front-end configured to receive image data and a first memory configured to store the image data. The ISP front-end is further configured to output the image data stored in the first memory to a second memory via a memory link in response to the image data stored in the first memory reaching a size threshold. Another apparatus includes apparatus includes a camera sensor configured to output image data in a camera mode, an ISP on a die, a camera link coupling the camera sensor and the ISP, a memory, and a memory link coupling the ISP and the memory. The memory link is configured to enter a low-power mode in the camera mode.

Abstract: Methods and systems to broadcast sensor outputs in an automotive environment allow sensors such as cameras to output relatively unprocessed (raw) data to two or more different processing circuits where the processing circuits are located in separate and distinct embedded control units (ECUs). A first one of the two or more different processing circuits processes the raw data for human consumption. A second one of the two or more different processing circuits processes the raw data for machine utilization such as for autonomous driving functions. Such an arrangement allows for greater flexibility in utilization of the data from the sensors without imposing undue latency in the processing stream and without compromising key performance indices for human use and machine use.

Abstract: Alternative display options for vehicle telltales are disclosed. In one aspect, a fault condition in a telltale is detected, and the telltale is presented through a secondary display system in the vehicle, potentially bypassing any local control unit for the secondary display system. For example, a video telltale may be presented on an infotainment display after detection of a fault in the original telltale. By presenting the telltale in an alternate display, the operator remains informed of sensor conditions in the automobile and may take remedial action to fix the fault as well as any conditions which trigger a telltale.

Abstract: An integrated circuit is disclosed for clock signal staggering with clock frequency adjustment. In an example aspect, the integrated circuit includes a clock source, a clock-signal controller, and a core. The clock source produces a core clock signal having a core frequency and performs an adjustment of the core frequency. The clock-signal controller generates a clock adjustment indicator signal indicative of the adjustment of the core frequency of the core clock signal. The core is coupled to the clock source and receives the core clock signal. The core includes multiple partitions that perform operations responsive to oscillation of the core clock signal at the core frequency. The core also includes clock stagger circuitry that is coupled to the clock-signal controller. The clock stagger circuitry sequentially provides the core clock signal to individual partitions of the multiple partitions based on the clock adjustment indicator signal.

Abstract: A system and method are disclosed for processing image data. An example method includes sequentially receiving a plurality of raster lines corresponding to an image, and grouping the plurality of raster lines into a plurality of full-scale horizontal stripes of image data. For each full-scale horizontal stripe of image data, the method: generates a first downscaled version of the full-scale horizontal stripe, generates a full-scale rotated stripe by rotating the full-scale horizontal stripe to a vertical orientation, generates a first downscaled rotated stripe by rotating the first downscaled version of the full-scale horizontal stripe to the vertical orientation, and performs image processing on the full-scale rotated stripe and the first downscaled rotated stripe before all subsequent raster lines of the image have been received.

Abstract: Various aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes initiating a memory transaction corresponding to first data. The method includes determining a non-unique first signature and a unique second signature associated with the first data based on content of the first data. The method includes determining if the non-unique first signature is stored in at least one of a local buffer on the SoC separate from the DRAM or the DRAM. The method includes determining if the unique second signature is stored in at least one of the local buffer or the DRAM based on determining the non-unique first signature is stored. The method includes eliminating the memory transaction with respect to the DRAM based on determining the unique second signature is stored.

Abstract: Systems and methods for switching voltage operating points of an image signal processing pipeline are provided. The method comprises capturing an image during a sensor frame time. The method further comprises storing a plurality of pixels associated with the captured image. The method further comprises reading a first set of plurality of pixels within the sensor frame time. The method further comprises processing the first set of plurality of pixels and count a first set of plurality of pixels. The method further comprises comparing the count value with a pixel threshold value. The method further comprises, in response to the pixel count value reaching the pixel threshold value, switching the image signal processing pipeline from a first voltage operating point to a second voltage operating point.

Abstract: Various aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes initiating a memory transaction corresponding to first data. The method includes determining a non-unique first signature and a unique second signature associated with the first data based on content of the first data. The method includes determining if the non-unique first signature is stored in at least one of a local buffer on the SoC separate from the DRAM or the DRAM. The method includes determining if the unique second signature is stored in at least one of the local buffer or the DRAM based on determining the non-unique first signature is stored. The method includes eliminating the memory transaction with respect to the DRAM based on determining the unique second signature is stored.

Abstract: Various embodiments of methods and systems for precompensated bus width conversion (“PBWC”) in a portable computing device (“PCD”) are disclosed. Because starting memory addresses for data transfers emanating from a processing engine in a system on a chip (“SoC”) may be misaligned with a starting memory address of a main bus on the SoC, PBWC solutions seek to precompensate data transfers to align the starting addresses. Advantageously, by doing so PBWC embodiments may significantly reduce the amount of “filler” data chunks that are transferred through the main bus, thereby optimizing band width utilization of the main bus.