Abstract: A spool configured to support a roll of material. The spool comprises an arbor, a first flange, and a second flange. The first flange includes a first plurality of flange panels that are rotatably connected to respective arbor panels of the arbor at a first arbor edge of the arbor. The second flange is connected to a second arbor edge of the arbor. The first flange is configured to transition between a retention configuration and an open configuration. In the retention configuration, the roll of material is substantially prevented from removal from the arbor along an arbor axis by the first and second flanges. In the open configuration, the roll of material is removable from the arbor and receivable on the arbor in the arbor direction.

Abstract: A method for transient analysis of a memory module circuit, the method including: determining port to port resistances between terminals of internal circuits of a plurality of leaf cells of a netlist representing the memory module circuit; generating a plurality of equivalent networks corresponding to the internal circuits of the leaf cells, the equivalent networks being connected to each other; promoting the equivalent networks of the leaf cells to a hierarchical level above the leaf cells in the netlist representing the memory module circuit; shorting one or more terminals of each of the leaf cells to a central node of a corresponding one of the equivalent networks; and performing the transient analysis of the leaf cells of the netlist representing the memory module circuit.

Abstract: In accordance with the present invention, there are provided fully human monoclonal antibodies against human cytotoxic T-lymphocyte antigen 4 (CTLA-4). Nucleotide sequences encoding and amino acid sequences comprising heavy and light chain immunoglobulin molecules, particularly contiguous heavy and light chain sequences spanning the complementarity determining regions (CDRs), specifically from within FR1 and/or CDR1 through CDR3 and/or within FR4, are provided. Further provided are antibodies having similar binding properties and antibodies (or other antagonists) having similar functionality as antibodies disclosed herein.

Abstract: Provided are methods and apparatus for enabling selective push processing during design and fabrication of an integrated circuit to improve performance of selected circuits of the integrated circuit. An exemplary method includes identifying a critical portion of an integrated circuit layout that defines a functional element having a critical operating frequency requirement and designing a subcircuit in the critical portion to enable performing a speed push process to increase performance of the subcircuit. The method can also include identifying at least one of a power supply node, a clock supply node, and an interface node at a boundary between the critical portion and a portion of the integrated circuit that is outside of the critical portion. The critical portion can be designed with a power domain that is independent of the portion of the integrated circuit that is outside of the critical portion.

Abstract: Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit.

Abstract: Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit.

Abstract: Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.

Abstract: Systems and methods for bi-modal and fine grained power delivery to an integrated circuit comprising functional blocks. A first power source is coupled to a functional block of the integrated circuit for supporting a first operating mode of the functional block. A second power source is coupled to the functional block for supporting a second operating mode of the functional block. The first and second operating modes can be high and low frequency modes respectively. The second power source can be derived from the first power source using on-die regulators or provided independently. A desired average throughput of the functional block can be achieved by controlling duty cycles of the first and second power sources.

Abstract: In accordance with the present invention, there are provided fully human monoclonal antibodies against human cytotoxic T-lymphocyte antigen 4 (CTLA-4). Nucleotide sequences encoding and amino acid sequences comprising heavy and light chain immunoglobulin molecules, particularly contiguous heavy and light chain sequences spanning the complementarity determining regions (CDRs), specifically from within FR1 and/or CDR1 through CDR3 and/or within FR4, are provided. Further provided are antibodies having similar binding properties and antibodies (or other antagonists) having similar functionality as antibodies disclosed herein.

Abstract: In accordance with the present invention, there are provided fully human monoclonal antibodies against human cytotoxic T-lymphocyte antigen 4 (CTLA-4). Nucleotide sequences encoding and amino acid sequences comprising heavy and light chain immunoglobulin molecules, particularly contiguous heavy and light chain sequences spanning the complementarity determining regions (CDRs), specifically from within FR1 and/or CDR1 through CDR3 and/or within FR4, are provided. Further provided are antibodies having similar binding properties and antibodies (or other antagonists) having similar functionality as antibodies disclosed herein.

Abstract: This disclosure describes novel systems, methods and software for providing flight training. In an aspect of some embodiments, flight data is collected during a training flight. That flight data then can be used to provide a review and/or simulation of the training flight. The student may be allowed to participate in the simulation by providing input from a set of controls. In some cases, an instructor (or another) might provide modified flight data, which can be used to modify the simulation. Advantageously, this allows for the analysis and simulation of a variety of hypothetical, “what-if” scenarios.

Abstract: In accordance with the present invention, there are provided fully human monoclonal antibodies against human cytotoxic T-lymphocyte antigen 4 (CTLA-4). Nucleotide sequences encoding and amino acid sequences comprising heavy and light chain immunoglobulin molecules, particularly contiguous heavy and light chain sequences spanning the complementarity determining regions (CDRs), specifically from within FR1 and/or CDR1 through CDR3 and/or within FR4, are provided. Further provided are antibodies having similar binding properties and antibodies (or other antagonists) having similar functionality as antibodies disclosed herein.

Abstract: Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.

Abstract: Systems and methods for bi-modal and fine grained power delivery to an integrated circuit comprising functional blocks. A first power source is coupled to a functional block of the integrated circuit for supporting a first operating mode of the functional block. A second power source is coupled to the functional block for supporting a second operating mode of the functional block. The first and second operating modes can be high and low frequency modes respectively. The second power source can be derived from the first power source using on-die regulators or provided independently. A desired average throughput of the functional block can be achieved by controlling duty cycles of the first and second power sources.

Abstract: Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.

Abstract: In accordance with the present invention, there are provided fully human monoclonal antibodies against human cytotoxic T-lymphocyte antigen 4 (CTLA-4). Nucleotide sequences encoding and amino acid sequences comprising heavy and light chain immunoglobulin molecules, particularly contiguous heavy and light chain sequences spanning the complementarity determining regions (CDRs), specifically from within FR1 and/or CDR1 through CDR3 and/or within FR4, are provided. Further provided are antibodies having similar binding properties and antibodies (or other antagonists) having similar functionality as antibodies disclosed herein.

Abstract: Systems and methods for adaptively mimicking wordline decoding logic for multi-voltage domain memory are disclosed. In one embodiment, the multi-voltage domain memory includes a memory array implemented in a high voltage domain and a multi-voltage domain control circuit. The multi-voltage domain control circuit includes multi-voltage domain decoding logic that generates a wordline for the memory array and a multi-voltage domain mimic logic that mimics the multi-voltage domain decoding logic to generate a dummy wordline. In one embodiment, the dummy wordline is utilized to trigger an ending edge (e.g., a falling edge) of the wordline once the wordline is asserted. In addition or alternatively, the dummy wordline is utilized to generate one or more control signals for the memory array such as, for example, a pre-charge control signal and/or a sense amplifier enable signal.

Abstract: Provided are methods and apparatus for enabling selective push processing during design and fabrication of an integrated circuit to improve performance of selected circuits of the integrated circuit. An exemplary method includes identifying a critical portion of an integrated circuit layout that defines a functional element having a critical operating frequency requirement and designing a subcircuit in the critical portion to enable performing a speed push process to increase performance of the subcircuit. The method can also include identifying at least one of a power supply node, a clock supply node, and an interface node at a boundary between the critical portion and a portion of the integrated circuit that is outside of the critical portion. The critical portion can be designed with a power domain that is independent of the portion of the integrated circuit that is outside of the critical portion.

Abstract: In accordance with the present invention, there are provided fully human monoclonal antibodies against human cytotoxic T-lymphocyte antigen 4 (CTLA-4). Nucleotide sequences encoding and amino acid sequences comprising heavy and light chain immunoglobulin molecules, particularly contiguous heavy and light chain sequences spanning the complementarity determining regions (CDRs), specifically from within FR1 and/or CDR1 through CDR3 and/or within FR4, are provided. Further provided are antibodies having similar binding properties and antibodies (or other antagonists) having similar functionality as antibodies disclosed herein.

Abstract: Power consumption in a Content Addressable Memory (CAM) circuit is reduced by use of a CAM circuit. According to one embodiment of the CAM circuit, the CAM circuit includes a plurality of match lines and match line restoration circuitry. The match line restoration circuitry is configured to prevent at least one of the match lines from being restored to a pre-evaluation state responsive to corresponding enable information.