Abstract: A device structure includes a first interconnect layer, a second interconnect layer, a device layer including a comprising a plurality of devices, where the device layer is between the first interconnect layer and the second interconnect layer. The device structure further includes a dielectric layer adjacent the second interconnect layer, where the dielectric layer includes one or more of metallic dopants or a plurality of metal structures, wherein the plurality of metal structures is electrically isolated from interconnect structures but in contact with a dielectric material of the second interconnect layer, and where the individual ones of the plurality of metal structures is above a region including at least some of the plurality of devices. The device structure further includes a substrate adjacent to the dielectric layer and a heat sink coupled with the substrate.

Abstract: Embodiments herein may describe techniques for an integrated circuit including a FinFET transistor to be used as an antifuse element having a path through a fin area to couple a source electrode and a drain electrode after a programming operation is performed. A FinFET transistor may include a source electrode in contact with a source area, a drain electrode in contact with a drain area, a fin area including silicon and between the source area and the drain area, and a gate electrode above the fin area and above the substrate. After a programming operation is performed to apply a programming voltage between the source electrode and the drain electrode to generate a current between the source electrode, the fin area, and the drain electrode, a path may be formed through the fin area to couple the source electrode and the drain electrode. Other embodiments may be described and/or claimed.

Abstract: Memory cell circuitry is disclosed. The memory cell circuitry includes a first transistor configured to have a threshold voltage of the first transistor modulated by hot carrier injection, a second transistor coupled to the first transistor and configured to have a threshold voltage of the second transistor modulated by hot carrier injection, a word line coupled to a gate of the first transistor and to a gate of the second transistor, a first bit line coupled to the first transistor and a second bit line coupled to the second transistor. In addition, the memory cell circuitry includes a source line coupled to the drain of the first transistor and to the drain of the second transistor, the word line and the source line configured to cause hot carrier injection (HCI) into the first transistor when a first supply voltage is applied to the word line and the source line, and the second bit line is floated and the first bit line is grounded.

Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate, an interlayer dielectric (ILD) layer above the metal interconnect with an opening to expose the metal interconnect at a bottom of the opening. A dielectric layer may conformally cover sidewalls and the bottom of the opening and in contact with the metal interconnect. An electrode may be formed within the opening, above the metal interconnect, and separated from the metal interconnect by the dielectric layer. After a programming voltage may be applied between the metal interconnect and the electrode to generate a current between the metal interconnect and the electrode, a conductive path may be formed through the dielectric layer to couple the metal interconnect and the electrode, changing the resistance between the metal interconnect and the electrode. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate and coupled to a first contact and a second contact. The first contact and the second contact may be above the metal interconnect and in contact with the metal interconnect. A first resistance may exist between the first contact and the second contact through the metal interconnect. After a programming voltage is applied to the second contact while the first contact is coupled to a ground terminal to generate a current between the first contact and the second contact, a non-conducting barrier may be formed as an interface between the second contact and the metal interconnect. A second resistance may exist between the first contact, the metal interconnect, the second contact, and the non-conducting barrier. Other embodiments may be described and/or claimed.

Abstract: Memory cell circuitry is disclosed. The memory cell circuitry includes a first transistor configured to have a threshold voltage of the first transistor modulated by hot carrier injection, a second transistor coupled to the first transistor and configured to have a threshold voltage of the second transistor modulated by hot carrier injection, a word line coupled to a gate of the first transistor and to a gate of the second transistor, a first bit line coupled to the first transistor and a second bit line coupled to the second transistor. In addition, the memory cell circuitry includes a source line coupled to the drain of the first transistor and to the drain of the second transistor, the word line and the source line configured to cause hot carrier injection (HCI) into the first transistor when a first supply voltage is applied to the word line and the source line, and the second bit line is floated and the first bit line is grounded.

Abstract: Embodiments herein may describe techniques for an integrated circuit including a FinFET transistor to be used as an antifuse element having a path through a fin area to couple a source electrode and a drain electrode after a programming operation is performed. A FinFET transistor may include a source electrode in contact with a source area, a drain electrode in contact with a drain area, a fin area including silicon and between the source area and the drain area, and a gate electrode above the fin area and above the substrate. After a programming operation is performed to apply a programming voltage between the source electrode and the drain electrode to generate a current between the source electrode, the fin area, and the drain electrode, a path may be formed through the fin area to couple the source electrode and the drain electrode. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate and coupled to a first contact and a second contact. The first contact and the second contact may be above the metal interconnect and in contact with the metal interconnect. A first resistance may exist between the first contact and the second contact through the metal interconnect. After a programming voltage is applied to the second contact while the first contact is coupled to a ground terminal to generate a current between the first contact and the second contact, a non-conducting barrier may be formed as an interface between the second contact and the metal interconnect. A second resistance may exist between the first contact, the metal interconnect, the second contact, and the non-conducting barrier. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate, an interlayer dielectric (ILD) layer above the metal interconnect with an opening to expose the metal interconnect at a bottom of the opening. A dielectric layer may conformally cover sidewalls and the bottom of the opening and in contact with the metal interconnect. An electrode may be formed within the opening, above the metal interconnect, and separated from the metal interconnect by the dielectric layer. After a programming voltage may be applied between the metal interconnect and the electrode to generate a current between the metal interconnect and the electrode, a conductive path may be formed through the dielectric layer to couple the metal interconnect and the electrode, changing the resistance between the metal interconnect and the electrode. Other embodiments may be described and/or claimed.

Abstract: A system and method for implementing an integrated information system are provided. A premises server is in communication with a variety of information sources that produce monitoring data for a premises. The premises server collects, presents, and transmits the monitoring device data to a central server capable of processing data from multiple premises servers. The central server receives the data and traverses one or more logical rule sets to determine whether the inputted data violates the rules. Based on an evaluation of the rules, the central server generates outputs in the form of communication to one or more authorized users via a variety of communication mediums and devices and/or the instigation of a variety of acts corresponding to the evaluation of the rules.

Abstract: A system and method for implementing an integrated information system are provided. A premises server is in communication with a variety of information sources that produce monitoring data for a premises. The premises server collects, presents, and transmits the monitoring device data to a central server capable of processing data from multiple premises servers. The central server receives the data and traverses one or more logical rule sets to determine whether the inputted data violates the rules. Based on an evaluation of the rules, the central server generates outputs in the form of communication to one or more authorized users via a variety of communication mediums and devices and/or the instigation of a variety of acts corresponding to the evaluation of the rules.

Abstract: A system and method for implementing an integrated information system are provided. A premises server is in communication with a variety of information sources that produce monitoring data for a premises. The premises server collects, presents, and transmits the monitoring device data to a central server capable of processing data from multiple premises servers. The central server receives the data and traverses one or more logical rule sets to determine whether the inputted data violates the rules. Based on an evaluation of the rules, the central server generates outputs in the form of communication to one or more authorized users via a variety of communication mediums and devices and/or the instigation of a variety of acts corresponding to the evaluation of the rules.

Abstract: A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents in succession.

Abstract: A system and method for implementing an integrated information system are provided. A premises server is in communication with a variety of information sources that produce monitoring data for a premises. The premises server collects, presents, and transmits the monitoring device data to a central server capable of processing data from multiple premises servers. The central server receives the data and traverses one or more logical rule sets to determine whether the inputted data violates the rules. Based on an evaluation of the rules, the central server generates outputs in the form of communication to one or more authorized users via a variety of communication mediums and devices and/or the instigation of a variety of acts corresponding to the evaluation of the rules.

Abstract: An embodiment of the present invention is a technique to program a fuse. A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents in succession.

Abstract: A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents in succession.

Abstract: An embodiment of the present invention is a technique to program a fuse. A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents in succession.

Abstract: The fluid delivery system includes a control console adapted to control delivery of fluid to a patient and a pump cassette disposed in a pump cassette socket in the control console and operatively controlled by the control console. The pump cassette includes a pump housing formed by opposing housing members that cooperatively define a pump chamber. A pair of meshed gears is disposed in the pump chamber and separate the pump chamber into a fluid inlet area and a fluid outlet area accessible through respective inlet and outlet ports in the pump housing. The gears are adapted to pressurize fluid for delivery to the patient. Other features of the system include a fluid heater upstream of the pump cassette, air detectors associated with the inlet and outlet ports of the pump cassette, and a sensor to read an encoding device associated with the pump cassette.

Abstract: An apparatus, a method, and a system for a fuse cell are disclosed herein. In various embodiments, a fuse cell may comprise a standby circuitry to reduce a voltage drop across a fuse device.

Abstract: Methods, systems and computer program products are provided for evaluating suitability of a network for packetized communications, including identifying devices on the network and obtaining a plurality of assessment rules selected to evaluate the suitability of the network. Configuration data is obtained from the identified devices and the plurality of assessment rules are automatically evaluated using the obtained configuration data to evaluate the suitability of the network.