Abstract: The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface. Such surface has a peripheral region received about a peripheral edge of the semiconductor substrate. A layer comprising amorphous carbon is provided over the substrate outer surface. A masking layer is provided outwardly of the amorphous carbon-comprising layer. A resist layer is provided outwardly of the masking layer. At least a portion of the peripheral region of the outer surface includes the amorphous carbon-comprising layer and the resist layer, but is substantially void of the masking layer. The amorphous carbon-comprising layer is patterned using the resist layer and the masking layer effective to form a mask over the semiconductor substrate. After the patterning, the semiconductor substrate is processed inwardly of the mask through openings formed in the mask.

Abstract: The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface. Such surface has a peripheral region received about a peripheral edge of the semiconductor substrate. A layer comprising amorphous carbon is provided over the substrate outer surface. A masking layer is provided outwardly of the amorphous carbon-comprising layer. A resist layer is provided outwardly of the masking layer. At least a portion of the peripheral region of the outer surface includes the amorphous carbon-comprising layer and the resist layer, but is substantially void of the masking layer. The amorphous carbon-comprising layer is patterned using the resist layer and the masking layer effective to form a mask over the semiconductor substrate. After the patterning, the semiconductor substrate is processed inwardly of the mask through openings formed in the mask.

Abstract: A method of forming a MOS transistor in an upper surface of a semiconductor substrate. A gate oxide layer covers the upper surface of the substrate. A gate stack comprising one or more thin film layers covers the gate oxide layer. A gate electrode pattern is partially etched into the gate stack, the partial etching step being completed before any of the gate oxide layer is exposed. Sidewall spacers are formed on edge surfaces of the partially formed gate electrode. Source and drain regions are created by ion implantation using the partially etched gate electrode and the sidewall spacers as a mask. The sidewall spacers are removed and lightly doped drain regions are formed by ion implantation using the partially etched gate electrode as a mask.

Abstract: A contact to a semiconductor substrate including a contact opening extending through an insulating layer to a doped active region of the semiconductor substrate. The contact opening can have a relatively high aspect ratio of 2:1 or greater. The contact further includes a refractory metal germanosilicide region at the bottom of the contact opening, a refractory metal germanide layer at the sidewalls of the contact opening, and an overlying refractory metal nitride layer. The refractory metals of the invention include at least tantalum, titanium, cobalt and mixtures thereof. The contact is metallized, preferably using tungsten or aluminum. The method of manufacturing the contact comprises etching the contact opening. A germane gas is used to clean native silicon dioxide from the bottom of the contact opening and to deposit a germanium layer thereon. A refractory metal layer is deposited over the germanium layer. After annealing in a nitrogen atmosphere at a temperature of about 600° C.

Abstract: A method is disclosed for forming a high aspect ratio submicron VLSI interconnect structure. The method makes use of the high diffusivity of aluminum alloyed with germanium and the low eutectic temperature of the alloy for more uniform filling of interconnect structure openings having high aspect ratios. The method comprises preparing a semiconductor device or portion of a semiconductor device that is to receive electrical contact, covering the semiconductor device with an insulating layer, forming an interconnect structure openings through the insulating layer, depositing a layer of germanium in the interconnect structure opening, and reflow sputtering aluminum or aluminum alloy into the interconnect structure opening. Alternatively, the aluminum or aluminum alloy can be cold sputtered into the interconnect structure opening, followed by a low temperature reflow. The aluminum will readily diffuse to the bottom of the interconnect structure opening, assisted by its high diffusivity with the germanium.

Abstract: A high aspect ratio submicron VLSI contact and corresponding method of manufacture is disclosed. The contact is formed through an insulative layer, such as silicon dioxide, to an underlying active region on a substrate of silicon wafer. The contact comprises a layer of titanium germanosilicide at the bottom of the contact opening, and a layer of titanium germanide at the sides of the contact opening, with an overlying layer of titanium nitride. The contact is metallized, preferably using tungsten or aluminum. The disclosed method of manufacturing the contact comprises first etching the contact opening, then exposing the bottom of the contact opening to germane gas to clean native silicon dioxide from the bottom of the contact opening. A 50 Angstrom layer of germanium is then deposited over the contact opening. A layer of titanium is then deposited over the germanium layer in the contact opening. The deposition of titanium is preferably accomplished using a collimator having an aspect ratio lower than about 2.

Abstract: A contact to a semiconductor substrate including a contact opening extending through an insulating layer to a doped active region of the semiconductor substrate. The contact opening can have a relatively high aspect ratio of 2:1 or greater. The contact further includes a refractory metal germanosilicide region at the bottom of the contact opening, a refractory metal germanide layer at the sidewalls of the contact opening, and an overlying refractory metal nitride layer. The refractory metals of the invention include at least tantalum, titanium, cobalt and mixtures thereof. The contact is metallized, preferably using tungsten or aluminum. The method of manufacturing the contact comprises etching the contact opening. A germane gas is used to clean native silicon dioxide from the bottom of the contact opening and to deposit a germanium layer thereon. A refractory metal layer is deposited over the germanium layer. After annealing in a nitrogen atmosphere at a temperature of about 600° C.

Abstract: A method is disclosed for forming a high aspect ratio submicron VLSI interconnect structure. The method makes use of the high diffusivity of aluminum alloyed with germanium and the low eutectic temperature of the alloy for more uniform filling of interconnect structure openings having high aspect ratios. The method comprises preparing a semiconductor device or portion of a semiconductor device that is to receive electrical contact, covering the semiconductor device with an insulating layer, forming an interconnect structure opening through the insulating layer, depositing a layer of germanium in the interconnect structure opening, and reflow sputtering aluminum or aluminum alloy into the interconnect structure opening. Alternatively, the aluminum or aluminum alloy can be cold sputtered into the interconnect structure opening, followed by a low temperature reflow. The aluminum will readily diffuse to the bottom of the interconnect structure opening, assisted by its high diffusivity with the germanium.

Abstract: A method is disclosed for forming a high aspect ratio submicron VLSI interconnect structure. The method makes use of the high diffusivity of aluminum alloyed with germanium and the low eutectic temperature of the alloy for more uniform filling of interconnect structure openings having high aspect ratios. The method comprises preparing a semiconductor device or portion of a semiconductor device that is to receive electrical contact, covering the semiconductor device with an insulating layer, forming an interconnect structure opening through the insulating layer, depositing a layer of germanium in the interconnect structure opening, and reflow sputtering aluminum or aluminum alloy into the interconnect structure opening. Alternatively, the aluminum or aluminum alloy can be cold sputtered into the interconnect structure opening, followed by a low temperature reflow. The aluminum will readily diffuse to the bottom of the interconnect structure opening, assisted by its high diffusivity with the germanium.

Abstract: A high aspect ratio submicron VLSI contact and corresponding method of manufacture is disclosed. The contact is formed through an insulative layer, such as silicon dioxide, to an underlying active region on a substrate of silicon wafer. The contact comprises a layer of titanium germanosilicide at the bottom of the contact opening, and a layer of titanium germanide at the sides of the contact opening, with an overlying layer of titanium nitride. The contact is metallized, preferably using tungsten or aluminum. The disclosed method of manufacturing the contact comprises first etching the contact opening, then exposing the bottom of the contact opening to germane gas to clean native silicon dioxide from the bottom of the contact opening. A 50 Angstrom layer of germanium is then deposited over the contact opening. A layer of titanium is then deposited over the germanium layer in the contact opening. The deposition of titanium is preferably accomplished using a collimator having an aspect ratio lower than about 2.