Abstract: An apparatus comprising a capacitor circuit, a control circuit, and a resistor circuit. The capacitor circuit may be configured to (i) be charged through an input terminal and (ii) store a charge sufficient to run a device on an output terminal. The control circuit may be configured to (i) charge the capacitor through the input terminal, (ii) couple the input terminal to a voltage source, and (iii) discharge the capacitor circuit when the output terminal is not connected to the device drive.

Abstract: An improved memory control and refresh apparatus as shown. For memory read operations, the read only memory and the random access memory are controlled by the NCSROM conductor (41) and the NCSRAM conductor (40), respectively, so that the read only memory and the random access memory do not compete for control of the data bus (20). However, the NCSRAM conductor (40) is not used to control the random access memory during write operations. Therefore, when transferring blocks of data from the read only memory (60) to the random access memory (61,62) the NCSROM conductor (41) is active during both reading of data from the read only memory (60) and writing of the data to the random access memory (61).

Abstract: An improved memory control and refresh apparatus as shown. For memory read operations, the read only memory and the random access memory are controlled by a signal on conductor (41) and a signal on conductor (40), respectively, so that the read only memory and the random access memory do not compete for control of the data bus (20). However, the signal on conductor (40) is not used to control the random access memory during write operations. Therefore, when transferring blocks of data from the read only memory (60) to the random access memory (61,62) the signal on conductor (41) is active during both reading of data from the read only memory (60) and writing of the data to the random access memory (61).

Abstract: A memory (90) comprising a non-volatile memory and a volatile memory, contains a test word and other words which represent a complete user-selected configuration profile. The configuration profile is stored in the memory (90) by a microprocessor (36) automatically when power is interrupted. A second power supply (80) provides operating power to the memory (90) so that the memory (90) can complete its storage cycle even after primary power has failed. The microprocessor (36) checks memory (90) for the test word to verify that the memory (90) has been programmed with a configuration profile and is not missing or defective. The modem (12) resets when power is first applied and when the power supply (75) noise exceeds a predetermined safe level. A concealed jumper strap (61) allows for the reversible placement of the modem (12) into a "dumb" mode wherein the configuration profile cannot be altered.