Abstract: A technique for forming a sub-0.05 &mgr;m channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive technique utilizes a damascene process for the fabrication of a MOSFET device with double-gate/double channel structure. The gates are present on opposite sides of a silicon film having a vertical thickness of about 80 nm or less which is present in the gate region. The silicon film serves as the vertical channel regions of the structure and connects diffusion regions that are abutting the gate region to each other. In the inventive device, the current is double that of a conventional planar MOSFET with the same physical width due to its dual channel feature.

Abstract: A method for manufacturing a semiconductor chip which has transistors is disclosed. The transistors include first type transistors which have a first type of doping and second type transistors which have a second type of doping different than the first type of doping. The method includes forming a conductive layer on a substrate. The conductive layer includes first regions that have the first type of doping and second regions have the second type of doping. The invention patterns a mask over the conductive layer, and the mask protects portions of the conductive layer where gate conductors will be located. Next, the invention partially etches unprotected portions of the conductive layer. The partially etching process allows a layer of the unprotected portions to remain, such that the substrate is not exposed by the partially etching process.

Abstract: Aspects of the invention are directed to monitoring a plurality of UPS devices coupled to a network. According to one aspect of the invention, a computer is coupled to the plurality of UPS devices through the network and monitors the states of the UPS devices by using a UPS devices monitoring icon. The UPS monitoring icon takes on various shapes depending on the status or state of one or more UPS devices being monitored and generally acts as an annunciator to the status or state. For example, the UPS monitoring icon 500 can take on one of four symbols depending on whether the UPS devices are operating normally or one or more UPS devices have been diagnosed as being in a “critical” state, a “warning” state or an “unknown” state.

Abstract: A technique for forming a sub-0.05 &mgr;m channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive technique utilizes a damascene process for the fabrication of a MOSFET device with double-gate/double channel structure. The gates are present on opposite sides of a silicon film having a vertical thickness of about 80 nm or less which is present in the gate region. The silicon film serves as the vertical channel regions of the structure and connects diffusion regions that are abutting the gate region to each other. In the inventive device, the current is double that of a conventional planar MOSFET with the same physical width due to its dual channel feature.

Abstract: A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched mask is then used as a hard mask for etching material on a lower layer.

Abstract: A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.

Abstract: A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.

Abstract: A method is described for lighting an inductive plasma in a plasma processing tool having a matching network, at pressures of about 20 mTorr and below. A matching condition for a capacitive plasma is determined, which then is used to define a match preset condition. When a plasma is started with the matching network in that preset condition, a capacitive plasma ignites and is maintained with a minimum of power. Excess power (power greater than that required to maintain the capacitive plasma) transfers the plasma to the inductive mode. The matching condition for the capacitive plasma may be determined by lighting a plasma, setting a power delivered thereto at not more than about 20 watts, and allowing the matching network to tune to the plasma. A capacitive plasma may be easily started at this preset condition. Current produced in the coil due to the excess power then causes the inductive plasma to light.

Abstract: A cleaning wafer is used during the vaporization of particulate deposits that were previously deposited on the walls of a plasma chamber. The cleaning wafer includes a first dielectric layer, a conducting layer and a second dielectric layer covering the conducting layer.

Abstract: An improved standing valve which regulates the amount of accumulated fluid in the tubing string of an oil and gas well, to an amount that is within the purging capability of the gas-lift method. The present invention provides a hydrostatic standing valve with a floating valve seat which is displaced in response to the weight of an accumulated fluid head. A ball seals against the floating valve seat and floats with it, but the displacement of the ball is limited by a positive stop provided by a rod supported by the standing valve body. When the valve seat displaces beyond that of the ball, as limited by the positive stop, the ball is sealingly disengaged from the valve seat and fluid flows out of the tubing string.

Abstract: In methods and apparatus for providing suppressed ringing access to a subscriber line, a connection request is sent from a server to a telecommunications switch and the switch performs a connection routine in response to the connection request to connect the server to the subscriber line. The connection routine is adapted to avoid audible ringing of a telephone set connected to the subscriber line. The connection request comprises a signal indicating a subscriber line to which the server is to be connected and a signal indicating that suppressed ringing access to that subscriber line is desired. The methods and apparatus avoid the need for especially provisioned trunks between the server and the terminating switches by including in the connection request a signal indicating that suppressed ringing is desired and by making the telecommunications switch responsive to that signal.

Abstract: A holding device (50) for securing two electrical articles (22,94) together includes a U-shaped leading end (52) having a pair of leg portions (54). The U-shaped end (52) and adjacent leg portions (60) define a spring means, adapted to be received in an aperture (96) of the second article (94). The legs (54) extend to free ends (70) and define a retaining section (73) adapted to be received into a recess (32) within a housing (24). The recess (32) includes a central wall portion (42) having leading engagement sites (44), which cooperate with inner leg edges (58) to secure the device (50) within the housing (24).

Abstract: An electrical connector assembly 10 includes a receptacle member 12 and a pin header 60. The receptacle member 12 has housing means 14 including an inner body portion 22 and two opposed outer side walls 24, which together define elongate cavities 36 between inner body section 22 and respective outer side walls 24; and a plurality of first contact terminal members 40 disposed in inner body portion 22 and a plurality of second contact terminal members 46 disposed in the elngate cavities 36.

Abstract: Data to be switched is preceded by a header containing routing information for establishing a connection via a switch, and is accompanied by additional information which indicates the start of the header, in response to which a connection is established, and the end of the data, in response to which the connection is terminated. The switch is a non-saturating, non-blocking, full matrix time switch which uses the routing information to establish a connection within one tdm frame, whereby connections for data of any type (including switch control information) and of arbitrary duration can be handled efficiently. An incoming channel can be connected to any free channel or to a specified outgoing channel of any output port, and contention resolution is provided for simultaneous requests for connection to a single outgoing channel. Interconnections among crosspoint nodes are reduced and simplified using token ring and systolic interconnection techniques.