Patents by Inventor Jeffrey J. Cronin
Jeffrey J. Cronin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9164937Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.Type: GrantFiled: March 24, 2014Date of Patent: October 20, 2015Assignee: Micron Technology, Inc.Inventors: Douglas A. Larson, Jeffrey J Cronin
-
Publication number: 20140207993Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.Type: ApplicationFiled: March 24, 2014Publication date: July 24, 2014Applicant: Micron Technology, Inc.Inventors: Douglas A. Larson, Jeffrey J. Cronin
-
Patent number: 8694735Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.Type: GrantFiled: September 12, 2012Date of Patent: April 8, 2014Assignee: Micron Technology, Inc.Inventors: Douglas A. Larson, Jeffrey J. Cronin
-
Publication number: 20130007384Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.Type: ApplicationFiled: September 12, 2012Publication date: January 3, 2013Inventors: Douglas A. Larson, Jeffrey J. Cronin
-
Patent number: 8291173Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.Type: GrantFiled: July 20, 2010Date of Patent: October 16, 2012Assignee: Micron Technology, Inc.Inventors: Douglas A. Larson, Jeffrey J. Cronin
-
Publication number: 20100287323Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.Type: ApplicationFiled: July 20, 2010Publication date: November 11, 2010Inventors: Douglas A. Larson, Jeffrey J. Cronin
-
Patent number: 7788451Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.Type: GrantFiled: February 5, 2004Date of Patent: August 31, 2010Assignee: Micron Technology, Inc.Inventors: Douglas A. Larson, Jeffrey J. Cronin
-
Patent number: 7774559Abstract: A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices. The memory hub operates in a second mode when the write command is not directed to the hub to provide the command's write data on a downstream output port adapted to be coupled to a downstream memory hub.Type: GrantFiled: August 27, 2007Date of Patent: August 10, 2010Assignee: Micron Technology, Inc.Inventors: Jeffrey J. Cronin, Douglas A. Larson
-
Patent number: 7363419Abstract: A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is directed to the hub to develop memory access signals adapted to be applied to memory devices. The memory hub operates in a second mode when the write command is not directed to the hub to provide the command's write data on a downstream output port adapted to be coupled to a downstream memory hub.Type: GrantFiled: May 28, 2004Date of Patent: April 22, 2008Assignee: Micron Technology, Inc.Inventors: Jeffrey J. Cronin, Douglas A. Larson
-
Patent number: 6128685Abstract: A method for terminating a bus configured to have one or more processors coupled thereto. The method comprises coupling a support member having a termination circuit thereon to a conductor of the bus. In one embodiment, the support member is connected to the bus separately from the processor. In another embodiment, the support member is coupled between the bus and the processor. The support member may include an auxiliary circuit in addition to the termination circuit and may be used to correct, supply, or update signals transmitted on the bus.Type: GrantFiled: February 18, 1998Date of Patent: October 3, 2000Assignee: Micron Technology, Inc.Inventor: Jeffrey J. Cronin
-
Patent number: 6122695Abstract: A device for terminating a bus configured to have one or more processors coupled thereto. The device comprises a support member having a termination circuit which is coupled to a conductor of the bus when the support member is coupled to the bus. In one embodiment, the support member is coupled between the bus and the processor. In another embodiment, the support member is connected to the bus separately from the processor. The support member may include an auxiliary circuit in addition to the termination circuit which may be used to correct, supply, or update signals transmitted on the bus.Type: GrantFiled: February 18, 1998Date of Patent: September 19, 2000Assignee: Micron Technology, Inc.Inventor: Jeffrey J. Cronin
-
Patent number: 5991837Abstract: Reversing the orientation of the processors in a dual-processor arrangement enables the overall length of the host bus to be reduced. In addition, less board layers may be required because the number of data and address/control bus crossovers is also reduced. Furthermore, the heat-dissipation surfaces of the processors may be aligned to face one another thereby forming a channel. This makes it more efficient to cool the processors because heat may be drawn away from each processor with a common fluid stream that can be propelled through the channel with a single fluid propeller.Type: GrantFiled: December 2, 1997Date of Patent: November 23, 1999Assignee: Micron Electronics, Inc.Inventors: Jeffrey J. Cronin, Travis J. Schaff