Abstract: A data storage device is disclosed comprising a first actuator configured to actuate a first head over a first disk, and a second actuator configured to actuate a second head over a second disk. The first actuator is controlled based on a first feed-forward seek profile to seek the first head over the first disk, and the second actuator is controlled to position the second head over a second data track on the second disk including to process the first feed-forward seek profile to attenuate a coupling disturbance from the first actuator.

Abstract: A method and system are described for performing an arithmetic operation such as multiplication or division of a fixed point variable measured at runtime by a floating point constant known at compile-time. The floating point constant is converted into a mantissa and a base-2 exponent at compile-time. The mantissa and exponent are preferably combined into a single unit (a word) of memory. At runtime either single multiplication and accumulation or matrix multiplication and accumulation is preferably achieved by a microprocessor or DSP instruction designed to use the mantissa-exponent pairs stored in a word of memory. The microprocessor instruction multiplies a fixed point runtime variable x by the mantissa and the result is shifted to the right or left as indicated by the exponent, which is preferably a 2's complement number. The complete instruction sequence to perform the multiplication can be made reentrant and can be pipelined.

Abstract: A method, apparatus and program storage device that provides a shift process with saturation for digital signal processor operations are disclosed. An instruction is generated for shifting an operand to either maximum or the minimum value depending on the bit of data input when saturation occurs. A saturation detection circuit is combined with an arithmetic shifter and a final decision multiplexor. The final decision multiplexor receives the output from the arithmetic shifter and the saturated value from the saturation circuit. When saturation is detected by the saturation detection circuit, the final decision multiplexor selects the saturate minimum or the saturate maximum depending on whether the MSB of the data in equals one or zero, respectively.

Abstract: A digital filter instruction and filter implementing the filter instruction are disclosed. The filter instruction synthesizes a digital filter and includes an instruction field, a tap length field, a coefficient address field, a data header address field, a clear accumulator bit and an update bit. The filter instruction a concise instruction format to significantly decrease memory required, allow for instruction pipelining without branch penalty, and uses a circular buffer for the data so the data address pointer is only needed to be updated for the next input sample. The filter instruction may be used to implement FIR or IIR filters by using the options of pre-clear accumulator or pre/post storing accumulator results.

Abstract: A method and apparatus for providing a processor based nested form polynomial engine are disclosed. A concise instruction format is provided to significantly decrease memory required and allow for instruction pipelining without branch penalty using a nested form polynomial engine. The instruction causing a processor to set coefficient and data address pointers for evaluating a polynomial, to load loading a coefficient and data operand into a coefficient register and a data register, respectively, to multiply the contents of the coefficient register and data register to produce a product, to add a next coefficient operand to the product to produce a sum, to provide the sum to an accumulator and to repeat the loading, multiplying, adding and providing until evaluation of the polynomial is complete.

Abstract: A method and system are described for performing an arithmetic operation such as multiplication or division of a fixed point variable measured at runtime by a floating point constant known at compile-time. The floating point constant is converted into a mantissa and a base-2 exponent at compile-time. The mantissa and exponent are preferably combined into a single unit (a word) of memory. At runtime either single multiplication and accumulation or matrix multiplication and accumulation is preferably achieved by a microprocessor or DSP instruction designed to use the mantissa-exponent pairs stored in a word of memory. The microprocessor instruction multiplies a fixed point runtime variable x by the mantissa and the result is shifted to the right or left as indicated by the exponent, which is preferably a 2's complement number. The complete instruction sequence to perform the multiplication can be made reentrant and can be pipelined.

Abstract: An apparatus and method of downloading data in the form of a device type generic “download entity” (or data object) for use by an electronic device. The device type of the electronic device is determined and any data in the download entity which is not associated with the determined device type is discarded such that only the data which is associated with the determined device type is retained by the electronic device. Installation code is also incorporated into the download entity such that, once downloaded, the installation code is executed by the electronic device to “unpack” and store the data associated with the device type from the download entity.

Abstract: An apparatus for calibrating a disk drive including a calibration circuit for calibrating parameters used in the operation of the disk drive. The system includes volatile storage for storing a personalized parameter value generated by the calibration circuit. The system also includes non-volatile storage for storing the personalized parameter value for subsequent use in calibrating the disk drive.

Abstract: An apparatus and method of downloading data in the form of a device type generic “download entity” (or data object) for use by an electronic device. The device type of the electronic device is determined and any data in the download entity which is not associated with the determined device type is discarded such that only the data which is associated with the determined device type is retained by the electronic device. Installation code is also incorporated into the download entity such that, once downloaded, the installation code is executed by the electronic device to “unpack” and store the data associated with the device type from the download entity.

Abstract: An apparatus and method of downloading data in the form of a device type generic “download entity” (or data object) for use by an electronic device. The device type of the electronic device is determined and any data in the download entity which is not associated with the determined device type is discarded such that only the data which is associated with the determined device type is retained by the electronic device. Installation code is also incorporated into the download entity such that, once downloaded, the installation code is executed by the electronic device to “unpack” and store the data associated with the device type from the download entity.

Abstract: A data recording disk drive is provided with a reassignment architecture that employs both an "in-line" approach for small disk defects and an "off-site" reassignment for multiple-sector defects. As a further aspect of the invention, the defective sites that have been off-site reassigned are periodically reinspected to determine whether they in fact remain defective. If it is determined upon inspection that the defect is no longer present, the data in the off-site reassign area is returned to its original location, freeing spares for reuse. As a further aspect of the invention, reinspection is performed at disk drive spin-up or during idle periods.

Abstract: A method and apparatus for mapping a physical track having more than a predetermined number of defective or spare sectors into two or more logical tracks to increase the number of defects the drive can handle in a constrained memory environment. The invention is particularly applicable to NoID.TM. disk drives. An interface processor is operatively coupled to a storage medium having concentric tracks for recording data therein. The interface processor maps physical tracks to logical tracks and determines whether defective and/or spare sectors exist in the physical track. The interface processor also redefines a physical track having more than a predetermined number of defective or spare sectors as at least one logical track. The at least one logical track has fewer than the predetermined number of defective or spare sectors within its boundaries. That is, a location for the defective and/or spare sectors is not mapped into the track detail. The dynamic track boundaries will change for each read or write.

Abstract: A DASD array and method wherein spindles in the array are synchronized in speed of rotation and phase. The invention includes a plurality of spindles and at least one disk rotating around each spindle, wherein each disk comprises a plurality of tracks arranged into synchronization zones. The synchronization zones comprise a plurality of data sectors and an excess time period associated with each zone. The excess time period comprises raw and synchronization skew, wherein the skew is used to shift sector locations in response to excessive defects occurring in the synchronization zone on the disk. In this manner, the phase of the disks in the system are synchronized without consuming additional disk storage capacity. Each disk also contains skip profiles for controlling the distribution of unused sectors across the disks. The skip profiles are distributed to model the defect profile in the worst disk in the system.