Abstract: Embodiments may provide a radiation hardened low-power data acquisition system-on-chip (SOC) suitable for space flight. The various embodiments may provide the radiation hardened low-power data acquisition SOC having a radiation hardened semiconductor die, a radiation hardened multiplexer integrated on the radiation hardened semiconductor die and configured to receive a plurality of analog signals and selectively output an analog signal of the plurality of analog signals, at least one radiation hardened analog to digital converted integrated on the radiation hardened semiconductor die and configured to convert the analog signal to a digital signal, and a radiation hardened serial communication interface integrated on the radiation hardened semiconductor die and configured to output the digital signal.

Abstract: The invention is a microcircuit configured as a compact, radiation hardened, low-power general purpose I/O expander. The expander may be controlled by an external microcontroller or central processing unit through a serial interface. The expander provides a simple solution to miniaturize static parallel I/O signals using a simplified serial interface such as I2C or SPI.

Abstract: A digital serial communication system includes a first serial communication circuit configured to exchange information utilizing a first communication protocol, a second serial communication circuit configured to exchange information utilizing a second communication protocol, and a common bus interface configured to couple the first serial communication circuit to a first serial communication bus implementing the first communication protocol, and configured to couple the second serial communication circuit to a second serial communication bus implementing the second communication protocol.

Abstract: A digital serial communication system includes a first serial communication circuit configured to exchange information utilizing a first communication protocol, a second serial communication circuit configured to exchange information utilizing a second communication protocol, and a common bus interface configured to couple the first serial communication circuit to a first serial communication bus implementing the first communication protocol, and configured to couple the second serial communication circuit to a second serial communication bus implementing the second communication protocol.

Abstract: The present invention is directed to a radiation-hardened by design quad amplifier in a commercial 0.25 ?m CMOS process; a 500 had total ionization dose (TID) (which degrades parts over time), and single event latchup immunity (SEL) which is greater than the linear energy transfer (LET) 120 MeV-sq. cm/mg; a single 3.3 V (range 3.0-3.6 V) power supply Vdd or dual power supply +/?1.65 V; four (4) channels of analog inputs; enhanced low-dose rate sensitivity (ELDRS) immunity; output rail-to-rail input/output (I/O) OPAMP which can drive resistive loads down to 1 kOhm; an active high enable pin en; a bias pin that can be used to adjust the OPAMP quiescent current; and a compact hermetic 16-lead ceramic small outline integrated circuit (SOIC) package.

Abstract: The present invention relates to a compact, low power, radiation-hardened-by-design 8-channel analog multiplexer ASIC, a 0.25 ?m complementary metal-oxide semiconductor (CMOS); a 500 krad total ionization dose and single event latchup which is greater than the linear energy transfer (LET) 120 MeV-sq. cm/mg; eight channels for 8-to-1 multiplexing; a three nanosecond break-before-make decoder; an active low enable pin; and an on-resistance of less than 500 ohms from input to output pads.

Abstract: Time-to-digital converters adapted to analog and digital inputs and methods of use are described. A time-to-digital converter has an event frame latches and logic module with memory cells, an analog front-end module connected to the memory cells, and a bin increment generator module connected to the memory cells. The bin increment generator is configured to issue bin increments separated by a time increment, and the analog front end is configured to issue a start event followed by a plurality of stop events. Upon receipt of a first time increment following a start event, the event frame latches and logic module updates a first memory cell with a first bit-type; upon receipt of a second time increment following an intervening stop event, the event frame latches and logic module updates a second memory cell with a second bit-type different from the first bit-type.

Abstract: Time-to-digital converters adapted to analog and digital inputs and methods of use are described. A time-to-digital converter has an event frame latches and logic module with memory cells, an analog front-end module connected to the memory cells, and a bin increment generator module connected to the memory cells. The bin increment generator is configured to issue bin increments separated by a time increment, and the analog front end is configured to issue a start event followed by a plurality of stop events. Upon receipt of a first time increment following a start event, the event frame latches and logic module updates a first memory cell with a first bit-type; upon receipt of a second time increment following an intervening stop event, the event frame latches and logic module updates a second memory cell with a second bit-type different from the first bit-type.

Abstract: An apparatus and method for imaging a target area is provided. Light is directed to a target area where it reflects off objects. The light is then returned to a receiving device. This receiving device creates a signal indicative of the intensity of the received light. The time of flight for the light plus the shape of the signal are analyzed to determine the range and shape of objects in the target area.