Abstract: A plurality of redundant rows/columns are added to a semiconductor memory array wherein each redundant row/column is located at a predetermined location in the memory array so as to divide the memory into equal sectors. Switches are utilized to connect the memory columns and rows and redundant memory columns and rows to row select, write circuitry, and read circuitry so that in the presence of a defective row or column, switches can be activated to remove the defective row or column from the array and to interconnect the remaining rows and columns in a predetermined adjacent pattern of interconnection. The controls for the switches comprise shift registers which are fully programmable and reprogrammable so that even through the memory array is configured to remove defective rows or columns at the point of manufacture, in the event of future defects occurring in the field, the shift registers can be reprogrammed to avoid future defective rows or columns.