Abstract: A hybrid storage device comprises at least one storage disk, a disk controller configured to control writing of data to and reading of data from the storage disk, a non-volatile electronic memory, and a bridge device coupled between the disk controller and the non-volatile electronic memory. The disk controller comprises a plurality of high-speed serial interfaces. In one embodiment, the high-speed serial interfaces include a first high-speed serial interface configured to interface the disk controller to a host device, and a second high-speed serial interface configured to interface the disk controller to the non-volatile memory via the bridge device. The non-volatile memory may comprise a flash memory, and the bridge device may comprise a flash controller. The disk controller may be implemented in the form of an SOC integrated circuit that is operative in a plurality of modes including a hybrid mode of operation and an enterprise mode of operation.

Abstract: A method and apparatus are provided for interfacing between a data source and a tightly-coupled memory. In the method and apparatus, a write data word and a write address are received from the data source and latched in a first clock cycle within a write buffer along a write data path, between the data source and the memory. The write data word is encoded according to an error detection code along the write data path. The write address and the write data word are applied to the memory from the write buffer. The write data word is accessible to the data source from the write data path or the memory beginning with a second clock cycle, which is a next subsequent clock cycle to the first clock cycle.

Abstract: An apparatus generally comprising a plurality of processors, a trace circuit, and a connector circuit. The trace circuit may be configured to present information at a port for debugging software in a selected processor of the processors. The connector circuit may be configured to (i) couple the trace circuit to the selected processor in response to a select signal and (ii) transfer the information from the selected processor to the trace circuit while the selected processor is executing the software.

Abstract: A data bus system transfers words and word portions on a data bus between master devices and slave devices. A size bus carries a size code in fixed-byte format that identifies a number of bytes being transferred in one or more words and/or word portions of a transaction. A byte-enable bus carries a byte-enable code that identifies valid bytes of a word. An interface decodes the byte-enable codes to size codes and, where an odd-byte byte-enable code is decoded, it decodes the odd-byte byte-enable code to a plurality of size codes.

Abstract: A data bus bridge circuit and method are provided for coupling a slave device with a data bus in a system in which data words are transferred between a master device and the slave device over the data bus. The bridge circuit removes master-induced stalls of burst transfers by converting those burst transfers into a plurality of separate, independent sub-bursts.

Abstract: A data bus bridge circuit and method are provided for coupling a slave device with a data bus in a system in which data words are transferred between a master device and the slave device over the data bus. The bridge circuit removes master-induced stalls of burst transfers by converting those burst transfers into a plurality of separate, independent sub-bursts.

Abstract: A system for controlling arbitration that may be used for a bus. The system generally comprises a bus, at least one master, and a first circuit coupled between the bus an the at least one master. The at least one master may be configured to present at least one transfer signal. The first circuit may be configured to (i) grant a bus mastership to a first master of the at least one master, (ii) present a first transfer signal of the at least one transfer signal to the bus in response to granting the bus mastership to the first master, (iii) remove the bus mastership from all masters of the at least one master, and (iv) present an idle transfer signal to the bus in response to removing the bus mastership from all masters.

Abstract: A method for controlling arbitration that may be used for a bus. The method generally comprises the steps of (A) controlling a bus mastership for the bus using a first arbitration scheme, (B) controlling the bus mastership using a second arbitration scheme in response to a first signal indicating a delay in a transfer between a first master of a plurality of masters and a slave on the bus, and (C) controlling the bus mastership using the first arbitration scheme in response to a second signal ending the delay in the transfer between the first master and the slave.

Abstract: A data bus system transfers words and word portions on a data bus between master devices and slave devices. A size bus carries a size code in fixed-byte format that identifies a number of bytes being transferred in one or more words and/or word portions of a transaction. A byte-enable bus carries a byte-enable code that identifies valid bytes of a word. An interface decodes the byte-enable codes to size codes and, where an odd-byte byte-enable code is decoded, it decodes the odd-byte byte-enable code to a plurality of size codes.

Abstract: A first-in-first-out (“FIFO”) buffer is provided for buffering communication data. The FIFO buffer includes a write port having a data input, an end-of-frame input and a write control input, a read port having a data output, an end-of-frame output and a read control input, and a plurality of storage locations. A write end-of-frame counter is coupled to the write port and has a write count output, which increments as a function of the end-of-frame input and the write control input. A read end-of-frame counter is coupled to the read port and has a read count output, which increments as a function of the end-of-frame output and the read control input. A comparator has a first compare input coupled to the write count output, a second compare input coupled to the read count output and a compare output indicating whether there is a data frame stored in the plurality of storage locations.

Abstract: A bus bridge generally comprising a first interface, a second interface, a plurality of registers and a controller. The first interface may be connectable to a first bus having a first data width. The second interface may be connectable to a second bus having a second data width narrower than the first data width. The plurality of registers may be configured to buffer (i) data, (ii) an address, and (iii) a plurality of control signals between the first bus and the second bus. The controller configured to control the registers.

Abstract: A data transmission buffer circuit is provided for buffering communication data, which is divided into a plurality of multiple-bit data frames that have a start and an end. The buffer circuit includes a first-in-first-out (FIFO) buffer and a frame counter. The FIFO buffer has a write port and a read port. The write port includes a data input, a write control input and an end-of-frame flag input, which indicates whether data on the data input includes the end of one of the data frames. The read port includes a data output, a read control input, and an end-of-frame flag output, which indicates whether data on the data output includes the end of one of the data frames. The frame counter is coupled to the write port and the read port and generates a frame count output that represents a number of the data frames stored in the FIFO buffer.

Abstract: A data conversion circuit and method are disclosed for converting an N-bit data stream to an M-bit data stream. A FIFO memory device having multiple N-bit memory locations receives as an input consecutive N-bit sets of data and stores each consecutively received N-bit set of data in consecutive memory locations. A write pointer identifies a next available memory location at which the next N-bit set of data is to be stored. A first read pointer identifies a first memory location containing a first portion of a first M-bit set of data. A second read pointer identifies a second memory location containing a last portion of the first M-bit set of data. Provided as the first M-bit set of data are each of the N-bit memory locations between and including the memory location identified by the first read pointer and the memory location identified by the second read pointer.

Abstract: A multiple channel data communication buffer includes a first side having a plurality of communication ports and a second side having data routing port. A single port transmit memory is coupled between the plurality of communication ports and the data routing port. A transmit arbitration circuit is coupled to the single port transmit memory, which arbitrates access by the plurality of communication ports and the data routing port to the single port transmit memory. A single port receive memory is coupled between the plurality of communication ports and the data routing port. A receive arbitration circuit coupled to the single port receive memory, which arbitrates access by the plurality of communication ports and the data routing port to the single port receive memory.

Abstract: A data communication circuit buffers data between a shared resource and a plurality of data communication interfaces through a plurality of respective first-in-first-out ("FIFO") buffers. The data is divided into multiple-bit data frames having a start and an end. The circuit maintains a priority level for each FIFO buffer and initializes the priority level of each FIFO buffer to a first priority level. The circuit passes bits of the multiple-bit data frames from the shared resource to respective ones of the FIFO buffers in a buffer order which is based on the priority level of each FIFO buffer. The circuit passes the bits from the FIFO buffers to the respective data communication interfaces and selectively increases the priority level of each FIFO buffer to a second, higher priority level as a function of a level the bits within the FIFO buffer and whether the end of at least one data frame is stored in the FIFO buffer.

Abstract: A transaction control circuit includes an initiate control circuit and a busy control circuit which are coupled between an initiate input, an initiate output, a busy input and busy output. The initiate control circuit sets the initiate output to an active state when the initiate input transitions from an inactive state to an active state and holds the initiate output in the active state until the initiate control circuit senses a transition in the busy input from an inactive state to an active state. The busy control circuit sets the busy output to an active state when either the initiate output is in the active state or the busy input is in the active state.