Abstract: Structures for a varactor diode and methods of forming same. The structure comprises a first semiconductor layer including a section on a substrate, a second semiconductor layer on the section of the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, and a doped region in the section of the first semiconductor layer. The section of the first semiconductor layer and the doped region have a first conductivity type, and the second semiconductor layer comprises silicon-germanium having a second conductivity type opposite to the first conductivity type, and the third semiconductor layer has the second conductivity type. The doped region contains a higher concentration of a dopant of the first conductivity type than the section of the first semiconductor layer. The second semiconductor layer abuts the first section of the first semiconductor layer along an interface, and the doped region is positioned adjacent to the interface.

Abstract: A method and structure for generating a boosted word line voltage for a memory array, such as a DRAM array. To ensure that an adequate voltage is applied to the word line of the memory array during write operations, the word line driver circuit is connected to a boost voltage generator which provides a substantially constant, regulated voltage which is boosted to a level which is approximately equal to the V.sub.cc supply voltage plus the threshold voltage of the memory cell pass transistor. A bias voltage generator provides a negative voltage which is used to bias the substrate of the memory array. The boosted voltage generator and the bias voltage generator can be operated in response to the same clock signal used to operate the memory array. A latch-up prevention circuit is provided to ensure that the word line driver circuit does not latch-up during power-on before an adequate boost voltage has been established.

Abstract: A method and structure for generating a boosted word line voltage for a memory array, such as a DRAM array. To ensure that an adequate voltage is applied to the word line of the memory array during write operations, the word line driver circuit is connected to a boost voltage generator which provides a substantially constant, regulated voltage which is boosted to a level which is approximately equal to the V.sub.CC supply voltage plus the threshold voltage of the memory cell pass transistor. A bias voltage generator provides a negative voltage which is used to bias the substrate of the memory array. The boosted voltage generator and the bias voltage generator can be operated in response to the same clock signal used to operate the memory array. A latch-up prevention circuit is provided to ensure that the word line driver circuit does not latch-up during power-on before an adequate boost voltage has been established.