Abstract: A voltage translator circuit (320) includes an input stage (322) adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch (326) adapted for connection to a second voltage supply (VDD33) and operative to at least temporarily store a logic state of the input signal, and a voltage clamp (324) coupled between the input stage (322) and the latch (326). The voltage clamp (322) is operative to set a maximum voltage across the latch (326) to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level. The voltage translator circuit (320) generates a first output signal (II) at a junction between the latch (326) and the voltage clamp (324). The voltage translator circuit generates a second output signal (15) at a junction between the voltage clamp (324) and the input stage (322).

Abstract: Disclosed is a bias circuit with a first resistor connected between the supply voltage and a feedback node. Resistors are connected in series between the feedback node and the reference supply voltage. The connections between the resistors define at least one bias voltage. A second resistor is connected between the feedback node and a first drain node. A first field-effect transistor has a first gate node, the first drain node, and a first source node. The gate node is connected to the first supply voltage. A second field-effect transistor has a second gate node, a second drain node, and a second source node. The second drain node is connected to the first source node. The second gate node is connected to the bias voltage. The second source node is connected to an output signal node. The output signal node capable of experiencing an overshoot voltage.

Abstract: Disclosed is a bias circuit with a first resistor connected between the supply voltage and a feedback node. Resistors are connected in series between the feedback node and the reference supply voltage. The connections between the resistors define at least one bias voltage. A second resistor is connected between the feedback node and a first drain node. A first field-effect transistor has a first gate node, the first drain node, and a first source node. The gate node is connected to the first supply voltage. A second field-effect transistor has a second gate node, a second drain node, and a second source node. The second drain node is connected to the first source node. The second gate node is connected to the bias voltage. The second source node is connected to an output signal node. The output signal node capable of experiencing an overshoot voltage.

Abstract: An integrated circuit comprises a resistor that is formed by doping a semiconductor region that is defined by a layer, typically polysilicon, that also defines the gate electrode of field effect transistors in the integrated circuit. The well-controlled linewidth of features defined in this layer provides for tight resistor tolerance, and also allows the value of the resistor to track changes in other features defined by this layer.

Abstract: A field effect transistor circuit generates a reference current that can obtain a desired temperature coefficient. The circuit is self-compensatory with respect to process variations, in that a "slow" process will produce a higher than normal current, while a "fast" process will give a lower one. This results in a tight spread of slew-rate, gain, gain-bandwidth, etc. in opamps, comparators, and other linear circuits. A simple adjustment in the circuit allows the temperature coefficient to be made positive or negative if so desired. An illustrative circuit is shown for CMOS technology, but can be applied to other field effect technologies.