Patents by Inventor Jeffrey J. Peterson

Jeffrey J. Peterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240124847
    Abstract: Disclosed herein are methods, compositions, kits, and agents useful for inducing ? cell maturation, and isolated populations of SC-? cells for use in various applications, such as cell therapy.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 18, 2024
    Inventors: Quinn P. Peterson, Felicia J. Pagliuca, Douglas A. Melton, Jeffrey Robert Millman, Michael Saris Segel, Mads Gurtler
  • Patent number: 11960615
    Abstract: The present disclosure generally relates to managing user profiles. An example method includes, at a computer system in communication with a display generation component and an input device: receiving, via the input device, a user input including a request to access a first restricted media item; and in response to the user input: in accordance with a determination the user input is a voice input and the voice input corresponds to a user profile authorized to access the first restricted media item using voice inputs, initiating playback of the first restricted media item; and in accordance with a determination the user input is a voice input and the voice input does not correspond to a user profile authorized to access the first restricted media item using voice inputs: forgoing initiating playback of the first restricted media item; and causing display, at the display generation component, of a validation user interface.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: April 16, 2024
    Assignee: Apple Inc.
    Inventors: Jeffrey Ma, Corey J. Peterson, Rob Bowles Sinclair, Hiu Yi Chan, Neil P. Cormican
  • Publication number: 20240101963
    Abstract: Disclosed herein are methods, compositions, kits, and agents useful for inducing ? cell maturation, and isolated populations of SC-? cells for use in various applications, such as cell therapy.
    Type: Application
    Filed: August 7, 2023
    Publication date: March 28, 2024
    Inventors: Quinn P. Peterson, Felicia J. Pagliuca, Douglas A. Melton, Jeffrey Robert Millman, Michael Saris Segel, Mads Gurtler, Alireza Rezania, Benjamin Fryer
  • Publication number: 20220388549
    Abstract: A railcar configured to transport a payload, the open-topped railcar including left and right sidewalls, forward and rear sidewalls, a left track, and a right track. The left and right sidewalls extend vertically from the floor and include upper edges. The forward and rear sidewalls extend vertically from the floor between the left and right sidewalls to form a payload bay. The left track is positioned near the left sidewall and spaced above the floor and below the upper edge of the left sidewall. The right track is positioned near the right sidewall and spaced above the floor and below the upper edge of the right sidewall. The left track and right track may include a number of pedestals spaced apart from each other and a number of ramps angled diagonally upward from some of the pedestals to upper edges of the forward and rear sidewalls. The left and right tracks are configured to support an independent material moving machine at least partially in the payload bay and/or between the left and right sidewalls.
    Type: Application
    Filed: June 8, 2021
    Publication date: December 8, 2022
    Applicant: OMAHA TRACK, INC.
    Inventor: Jeffrey J. Peterson
  • Patent number: 8617707
    Abstract: Disclosed herein are magic size nanoclusters comprising lead and one or more chalcogens. The disclosed magic size nanoclusters have both spectrally narrow fluorescence and ultra-high quantum efficiencies. Further disclosed herein is a method for preparing PbS, PbSe, and PbTe magic size nanoclusters. The yield of magic size nanoclusters can be increased by using anion sources enriched for secondary phosphines. The use of enriched secondary phosphine anion sources also increases the yield of quantum nanostructures.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: December 31, 2013
    Assignee: University of Rochester
    Inventors: Todd D. Krauss, Christopher Evans, Li Guo, Jeffrey J. Peterson
  • Publication number: 20110052918
    Abstract: Disclosed herein are magic size nanoclusters comprising lead and one or more chalcogens. The disclosed magic size nanoclusters have both spectrally narrow fluorescence and ultra-high quantum efficiencies. Further disclosed herein is a method for preparing PbS, PbSe, and PbTe magic size nanoclusters. The yield of magic size nanoclusters can be increased by using anion sources enriched for secondary phosphines. The use of enriched secondary phosphine anion sources also increases the yield of quantum nanostructures.
    Type: Application
    Filed: March 24, 2009
    Publication date: March 3, 2011
    Inventors: Todd D. Krauss, Christopher Evans, Li Guo, Jeffrey J. Peterson
  • Patent number: 6972245
    Abstract: One embodiment of the present invention provides a system for co-fabricating strained and relaxed crystalline, poly-crystalline, and amorphous structures in an integrated circuit device using common fabrication steps. The system operates by first receiving a substrate. The system then fabricates multiple layers on this substrate. A layer within these multiple layers includes both strained structures and relaxed structures. These strained structures and relaxed structures are fabricated simultaneously using common fabrication steps.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: December 6, 2005
    Assignee: The Regents of the University of California
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Patent number: 6884640
    Abstract: One embodiment of the present invention provides a system that determines the composition of a layer within an integrated device. The system operates by first receiving the integrated device. Next, the system measures properties of the layer using electromagnetic radiation. The properties of the layer measured are used to determine an index of refraction for the layer. The system then solves for the composition of the layer using the index of refraction.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: April 26, 2005
    Assignee: The Regents of the University of California
    Inventors: Jeffrey J. Peterson, Charles E. Hunt, Peter J. Bjeletich
  • Patent number: 6818137
    Abstract: One embodiment of the present invention provides a system that facilitates construction of electromagnetic, optical, chemical, and mechanical systems using chemical endpoint detection. The system operates by receiving a system description that specifies multiple components, including a first component and a second component. The system fabricates the first component and the second component using selected construction materials. The system also creates a first interconnection structure on the first component and a second interconnection structure on the second component. These interconnection structures can be created using a sacrificial layer and chemical endpoint detection. Next, the system brings the first component and the second component together by connecting the first interconnection structure and the second interconnection structure. These interconnection structures align the first component to the second component so that accurate alignment can be achieved.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: November 16, 2004
    Assignee: The Regents of the University of California
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Patent number: 6800212
    Abstract: One embodiment of the present invention provides a system to facilitate using selective etching to form optical components on a circuit device. The system operates by receiving a substrate composed of a first material including a buffer layer composed of a second material. The system forms a sacrificial layer composed of a third material on the buffer layer. Next, the system forms an optical fiber core composed of a fourth material on the sacrificial layer. After the optical fiber core has been formed, the system performs an etching operation using a selective etchant to remove the sacrificial layer. The system also applies a cladding layer to the optical fiber core.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: October 5, 2004
    Assignee: The Regents of the University of California
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Publication number: 20040014250
    Abstract: One embodiment of the present invention provides a system that determines the composition of a layer within an integrated device. The system operates by first receiving the integrated device. Next, the system measures properties of the layer using electromagnetic radiation. The properties of the layer measured are used to determine an index of refraction for the layer. The system then solves for the composition of the layer using the index of refraction.
    Type: Application
    Filed: May 13, 2003
    Publication date: January 22, 2004
    Inventors: Jeffrey J. Peterson, Charles E. Hunt, Peter J. Bjeletich
  • Publication number: 20030219937
    Abstract: One embodiment of the present invention provides a system for co-fabricating strained and relaxed crystalline, poly-crystalline, and amorphous structures in an integrated circuit device using common fabrication steps. The system operates by first receiving a substrate. The system then fabricates multiple layers on this substrate. A layer within these multiple layers includes both strained structures and relaxed structures. These strained structures and relaxed structures are fabricated simultaneously using common fabrication steps.
    Type: Application
    Filed: May 15, 2003
    Publication date: November 27, 2003
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Publication number: 20030215968
    Abstract: One embodiment of the present invention provides a system to facilitate using selective etching to form optical components on a circuit device. The system operates by receiving a substrate composed of a first material including a buffer layer composed of a second material. The system forms a sacrificial layer composed of a third material on the buffer layer. Next, the system forms an optical fiber core composed of a fourth material on the sacrificial layer. After the optical fiber core has been formed, the system performs an etching operation using a selective etchant to remove the sacrificial layer. The system also applies a cladding layer to the optical fiber core.
    Type: Application
    Filed: May 15, 2002
    Publication date: November 20, 2003
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Publication number: 20030213769
    Abstract: One embodiment of the present invention provides a system that facilitates construction of electromagnetic, optical, chemical, and mechanical systems using chemical endpoint detection. The system operates by receiving a system description that specifies multiple components, including a first component and a second component. The system fabricates the first component and the second component using selected construction materials. The system also creates a first interconnection structure on the first component and a second interconnection structure on the second component. These interconnection structures can be created using a sacrificial layer and chemical endpoint detection. Next, the system brings the first component and the second component together by connecting the first interconnection structure and the second interconnection structure. These interconnection structures align the first component to the second component so that accurate alignment can be achieved.
    Type: Application
    Filed: May 15, 2002
    Publication date: November 20, 2003
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Patent number: 6651032
    Abstract: Programming a reference voltage in a reference cell of a charge-based memory to a level that will maximize the predicted operational life of the memory, based on the application-specific predicted usage profile of the memory and the effects of that usage profile on the leakage curves of the various memory states. The different states of a memory cell may have different leakage rates, based on operational and environmental considerations, causing the cell to fail prematurely in one state, while having significant remaining life in the other state(s). The operational life of the memory can be increased by adjusting the reference threshold voltage so that the faster-leaking sate will last longer before failure occurs. Maximum operational life can be achieved by setting the reference voltage to maximize the predicted time-to-failure of the state with the shortest predicted time-to-failure.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: November 18, 2003
    Assignee: Intel Corporation
    Inventors: Jeffrey J. Peterson, David M. Dixon, Dow Ping D. Wong
  • Patent number: 6642154
    Abstract: One embodiment of the present invention provides a process for selective etching during semiconductor manufacturing. The process starts by receiving a silicon substrate with a first layer composed of a first material, which is covered by a second layer composed of a second material. The process then performs a first etching operation that etches some but not all of the second layer, so that a portion of the second layer remains covering the first layer. Next, the system performs a second etching operation to selectively etch through the remaining portion of the second layer using a selective etchant. The etch rate of the selective etchant through the second material is faster than an etch rate of the selective etchant through the first material, so that the second etching operation etches through the remaining portion of the second layer and stops at the first layer.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: November 4, 2003
    Assignee: The Regents of the University of California
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Patent number: 6559058
    Abstract: One embodiment of the present invention provides a system for using selective etching to form three-dimensional components on a substrate. The system operates by receiving a substrate composed of a first material. Next, a second layer composed of a second material is formed on selected portions of the substrate. A third layer composed of a third material is then formed over the substrate and the second layer. Finally, an etching operation using a selective etchant is used to remove the second layer, thereby leaving the substrate, which forms a first active layer, and leaving the third layer, which forms a second active layer.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: May 6, 2003
    Assignee: The Regents of the University of California
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Patent number: 6545299
    Abstract: One embodiment of the present invention provides a process that uses selective etching to form a structure on a silicon substrate. The process starts by receiving the silicon substrate with a first layer composed of a first material, which includes voids created by a first etching operation. The process then forms a second layer composed of a second material over the first layer, so that the second layer fills in portions of voids in the first layer created by the first etching operation. Next, the process performs a chemo-mechanical polishing operation on the second layer down to the first layer so that only remaining portions of the second layer, within the voids created by the first etching operation, remain.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: April 8, 2003
    Assignee: The Regents of the University of California
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Publication number: 20030008519
    Abstract: One embodiment of the present invention provides a process for selective etching during semiconductor manufacturing. The process starts by receiving a silicon substrate with a first layer composed of a first material, which is covered by a second layer composed of a second material. The process then performs a first etching operation that etches some but not all of the second layer, so that a portion of the second layer remains covering the first layer. Next, the system performs a second etching operation to selectively etch through the remaining portion of the second layer using a selective etchant. The etch rate of the selective etchant through the second material is faster than an etch rate of the selective etchant through the first material, so that the second etching operation etches through the remaining portion of the second layer and stops at the first layer.
    Type: Application
    Filed: July 5, 2001
    Publication date: January 9, 2003
    Inventors: Jeffrey J. Peterson, Charles E. Hunt
  • Patent number: RE42551
    Abstract: A flash memory device including a first memory array, a control circuit coupled to the first memory array, and a second independent memory array coupled to the control circuit. The first memory array includes a plurality of memory blocks each having a memory cell. The memory cell may be a nonvolatile flash memory cell. The control circuit controls the programming, erasing, and reading of the memory cells. The second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates whether the memory cell in the corresponding memory block is locked. The second memory array may also include a master lock-bit that indicates whether the block lock-bits are locked.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: July 12, 2011
    Inventors: Vishram Prakash Dalvi, Rodney R. Rozman, Christopher John Haid, Jerry Kreifels, Joseph Tsang, Jeff Evertt, Jahanshir J. Javanifard, Jeffrey J. Peterson