Abstract: A multi-level voltage regulator system/method providing discrete regulation of a DC-DC intermediate bus converter (IBC) output voltage (Vout) is disclosed. The disclosed system/method allows IBC Vout to be regulated in discrete steps during periods where IBC input voltage (Vin) falls below nominal operating values. Rather than shutting down or degrading IBC Vout in an unpredictable non-linear fashion based on IBC input/loading, IBC Vout is regulated in fixed discrete steps, allowing IBC-connected point-of-load (POL) converters to obtain stable power input that is well-defined over IBC Vin. IBC operating parameters may define multi-dimensional operational state spaces of IBC Vout regulation that ensure optimum power flow to attached POLs while maintaining operational stability within the IBC regulator. Instabilities in IBC/POL performance across variations in IBC Vin, load transients, POL loading, and environmental variables may be prevented using Vin voltage step hysteresis.

Abstract: A multi-level voltage regulator system/method providing discrete regulation of a DC-DC intermediate bus converter (IBC) output voltage (Vout) is disclosed. The disclosed system/method allows IBC Vout to be regulated in discrete steps during periods where IBC input voltage (Vin) falls below nominal operating values. Rather than shutting down or degrading IBC Vout in an unpredictable non-linear fashion based on IBC input/loading, IBC Vout is regulated in fixed discrete steps, allowing IBC-connected point-of-load (POL) converters to obtain stable power input that is well-defined over IBC Vin. IBC operating parameters may define multi-dimensional operational state spaces of IBC Vout regulation that ensure optimum power flow to attached POLs while maintaining operational stability within the IBC regulator. Instabilities in IBC /POL performance across variations in IBC Vin, load transients, POL loading, and environmental variables may be prevented using Vin voltage step hysteresis.

Abstract: A multi-level voltage regulator system/method providing discrete regulation of a DC-DC intermediate bus converter (IBC) output voltage (Vout) is disclosed. The disclosed system/method allows IBC Vout to be regulated in discrete steps during periods where IBC input voltage (Vin) falls below nominal operating values. Rather than shutting down or degrading IBC Vout in an unpredictable non-linear fashion based on IBC input/loading, IBC Vout is regulated in fixed discrete steps, allowing IBC-connected point-of-load (POL) converters to obtain stable power input that is well-defined over IBC Vin. IBC operating parameters may define multi-dimensional operational state spaces of IBC Vout regulation that ensure optimum power flow to attached POLs while maintaining operational stability within the IBC regulator. Instabilities in IBC/POL performance across variations in IBC Vin, load transients, POL loading, and environmental variables may be prevented using Vin voltage step hysteresis.

Abstract: The present invention provides a DC-DC power converter that comprises two or more Printed Wiring Boards (PWB) mounted parallel to one another and without encapsulation. Electronic components can be mounted on both sides of each board. The open design and parallel orientation of the PWBs allow airflow over components mounted on the PWBs. The PWBs are preferable made of FR-4 with copper foils, with one thicker board being comprised of more copper layers and the other boards comprised of less copper layers. In the preferred embodiment, the power processing elements are housed in the thicker PWB, while the thinner boards house the control circuitry.

Abstract: A multi-level voltage regulator system/method providing discrete regulation of a DC-DC intermediate bus converter (IBC) output voltage (Vout) is disclosed. The disclosed system/method allows IBC Vout to be regulated in discrete steps during periods where IBC input voltage (Vin) falls below nominal operating values. Rather than shutting down or degrading IBC Vout in an unpredictable non-linear fashion based on IBC input/loading, IBC Vout is regulated in fixed discrete steps, allowing IBC-connected point-of-load (POL) converters to obtain stable power input that is well-defined over IBC Vin. IBC operating parameters may define multi-dimensional operational state spaces of IBC Vout regulation that ensure optimum power flow to attached POLs while maintaining operational stability within the IBC regulator. Instabilities in IBC/POL performance across variations in IBC Vin, load transients, POL loading, and environmental variables may be prevented using Vin voltage step hysteresis.

Abstract: The present invention provides a DC-DC power converter that comprises two or more Printed Wiring Boards (PWB) mounted parallel to one another and without encapsulation. Electronic components can be mounted on both sides of each board. The open design and parallel orientation of the PWBs allow airflow over components mounted on the PWBs. The PWBs are preferable made of FR-4 with copper foils, with one thicker board being comprised of more copper layers and the other boards comprised of less copper layers. In the preferred embodiment, the power processing elements are housed in the thicker PWB, while the thinner boards house the control circuitry.

Abstract: A control scheme for a synchronous rectifier converter that avoids disabling the synchronous rectifiers entirely. Rather than disable the synchronous rectifier altogether to stop the flow of reverse current in light-load, startup, or shutdown conditions, the duty cycle of the synchronous rectifier is modified such that forward current is always allowed to flow through the synchronous rectifier, but the synchronous rectifier is turned off before the reverse current flow reaches a pre-determined level. This is accomplished by operating the converter in a partially synchronous mode of operation during light-load, startup, or shutdown conditions. Whether the circuit is in a light-load, startup, or shutdown condition is determined by a circuit characteristic of the converter that is sensed by the controller, such as average output current. The desired changeover point from fully-synchronous mode to the partially synchronous mode is set to a predetermined level of output current for the converter.

Abstract: A control scheme for a synchronous rectifier converter that avoids disabling the synchronous rectifiers entirely. Rather than disable the synchronous rectifier altogether to stop the flow of reverse current in light-load, startup, or shutdown conditions, the duty cycle of the synchronous rectifier is modified such that forward current is always allowed to flow through the synchronous rectifier, but the synchronous rectifier is turned off before the reverse current flow reaches a pre-determined level. This is accomplished by operating the converter in a partially synchronous mode of operation during light-load, startup, or shutdown conditions. Whether the circuit is in a light-load, startup, or shutdown condition is determined by a circuit characteristic of the converter that is sensed by the controller, such as average output current. The desired changeover point from fully-synchronous mode to the partially synchronous mode is set to a predetermined level of output current for the converter.

Abstract: An architecture for a post regulator control circuit that utilizes an advance trigger signal to trigger the post regulator ramp. This advance trigger signal anticipates the beginning and end of a power cycle, and can be used to drive all of the secondary rectifier switches with optimal timing to minimize both cross conduction and body diode conduction. The architecture can be used to cascade an arbitrary number of post regulators. The present invention provides to the auxiliary outputs the full range of regulation available to the main output even in light load conditions. Rather than sensing the beginning or end of the power cycle, the present invention anticipates the beginning and end of the power cycle using the pulse train generated by the feedback loop for the main output. This allows the circuit to prepare the switches for the beginning of the power cycle and avoids problems encountered with inherent propagation delays in the circuit.