Patents by Inventor Jeffrey John Pream
Jeffrey John Pream has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11429315Abstract: Systems and methods are disclosed for command status polling at a flash queue of a non-volatile memory device. The flash queue may be configured to perform polling on the status of flash operations without direct oversight from the data storage controller or firmware. In certain embodiments, a flash queue circuit may be configured to receive, from a data storage controller of a nonvolatile solid state memory (NVSSM) data storage device, one or more commands to access a flash memory of the NVSSM data storage device, each command of the one or more commands including one or more instructions. The flash queue circuit may execute the one or more commands to access the flash memory, evaluate a status response from the flash memory at the flash queue circuit, and re-execute a sequence of instructions of the one or more commands based on the status response.Type: GrantFiled: September 10, 2020Date of Patent: August 30, 2022Assignee: Seagate Technology LLCInventors: Jeffrey John Pream, Jeremy Blair Goolsby
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Patent number: 11233528Abstract: A low-density parity check (LDPC) decoder includes a variable node unit (VNU) comprising a plurality of variable nodes configured to perform sums. A first message mapper of the LDPC decoder receives first n1-bit indices from likelihood ratio (LLR) input and maps the first n1-bit indices to first numerical values that are input to the variable nodes of the VNU. A second message mapper of the LDPC decoder receives second n2-bit indices from a check node unit (CNU) and maps the second n2-bit indices to second numerical values that are input to the variable nodes of the VNU. The CNU includes a plurality of check nodes that perform parity check operations. The first and second numerical values having ranges that are larger than what can be represented in n1-bit and n2-bit binary, respectively.Type: GrantFiled: September 16, 2020Date of Patent: January 25, 2022Assignee: Seagate Technology LLCInventors: Ivana Djurdjevic, Ara Patapoutian, Deepak Sridhara, Bengt Anders Ulriksson, Jeffrey John Pream
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Patent number: 10802756Abstract: Systems and methods are disclosed for command status polling at a flash queue of a non-volatile memory device. The flash queue may be configured to perform polling on the status of flash operations without direct oversight from the data storage controller or firmware. In certain embodiments, a flash queue circuit may be configured to receive, from a data storage controller of a nonvolatile solid state memory (NVSSM) data storage device, one or more commands to access a flash memory of the NVSSM data storage device, each command of the one or more commands including one or more instructions. The flash queue circuit may execute the one or more commands to access the flash memory, evaluate a status response from the flash memory at the flash queue circuit, and re-execute a sequence of instructions of the one or more commands based on the status response.Type: GrantFiled: July 12, 2018Date of Patent: October 13, 2020Assignee: Seagate Technology LLCInventors: Jeffrey John Pream, Jeremy Blair Goolsby
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Publication number: 20190007070Abstract: Method and apparatus for managing data decoder circuits, such as LDPC (low density parity check) decoders in a solid state drive (SSD). In some embodiments, a non-volatile memory (NVM) is configured to store data in the form of code words. Each code word has a user data payload and associated code bits. A plurality of data decoder circuits are configured to use the code bits to detect and correct bit errors in the code words during a read operation. A power transition circuit is configured to successively transition each of the data decoder circuits in turn from a first power mode to a second power mode, such as from an active mode to an idle mode, at a different time and at a conclusion of a predetermined time interval. In this way, voltage spikes or other anomalous conditions on a voltage source pathway may be reduced.Type: ApplicationFiled: July 3, 2017Publication date: January 3, 2019Inventors: Jeffrey John Pream, Eric Michael Beck
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Patent number: 10171110Abstract: Method and apparatus for managing data decoder circuits, such as LDPC (low density parity check) decoders in a solid state drive (SSD). In some embodiments, a non-volatile memory (NVM) is configured to store data in the form of code words. Each code word has a user data payload and associated code bits. A plurality of data decoder circuits are configured to use the code bits to detect and correct bit errors in the code words during a read operation. A power transition circuit is configured to successively transition each of the data decoder circuits in turn from a first power mode to a second power mode, such as from an active mode to an idle mode, at a different time and at a conclusion of a predetermined time interval. In this way, voltage spikes or other anomalous conditions on a voltage source pathway may be reduced.Type: GrantFiled: July 3, 2017Date of Patent: January 1, 2019Assignee: Seagate Technology LLCInventors: Jeffrey John Pream, Eric Michael Beck
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Patent number: 9323584Abstract: A load adaptive pipeline system includes a data recovery pipeline configured to transfer data between a memory and a host. The pipeline includes a plurality of resources, one or more of the plurality of resources in the pipeline have multiple resource components available for allocation. The system includes a pipeline controller configured to assess at least one parameter affecting data transfer through the pipeline. The pipeline controller is configure to allocate resource components to the one or more resources in the pipeline in response to assessment of the at least one data transfer parameter.Type: GrantFiled: September 6, 2013Date of Patent: April 26, 2016Assignee: SEAGATE TECHNOLOGY LLCInventors: Jeffrey John Pream, Bijoy Purushothaman, Venugopal Rao Garuda, Ara Patapoutian
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Patent number: 9280422Abstract: A device comprising a data transfer channel is configured to transfer data between multiple memory devices and a host device. The channel includes multiple decoders and a buffer coupled between the multiple memory devices and the multiple decoders. The buffer is configured to store code words received from the memory devices. Channel control logic is configured to determine availability of one or more of the multiple decoders and to distribute the code words to the one or more decoders based on decoder availability.Type: GrantFiled: September 6, 2013Date of Patent: March 8, 2016Assignee: SEAGATE TECHNOLOGY LLCInventors: Jeffrey John Pream, Ara Patapoutian
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Publication number: 20150074677Abstract: A load adaptive pipeline system includes a data recovery pipeline configured to transfer data between a memory and a host. The pipeline includes a plurality of resources, one or more of the plurality of resources in the pipeline have multiple resource components available for allocation. The system includes a pipeline controller configured to assess at least one parameter affecting data transfer through the pipeline. The pipeline controller is configure to allocate resource components to the one or more resources in the pipeline in response to assessment of the at least one data transfer parameter.Type: ApplicationFiled: September 6, 2013Publication date: March 12, 2015Applicant: Seagate Technology LLCInventors: Jeffrey John Pream, Purushothaman Bijoy, Venugopal Rao Garuda, Ara Patapoutian
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Publication number: 20150074488Abstract: A device comprising a data transfer channel is configured to transfer data between multiple memory devices and a host device. The channel includes multiple decoders and a buffer coupled between the multiple memory devices and the multiple decoders. The buffer is configured to store code words received from the memory devices. Channel control logic is configured to determine availability of one or more of the multiple decoders and to distribute the code words to the one or more decoders based on decoder availability.Type: ApplicationFiled: September 6, 2013Publication date: March 12, 2015Applicant: Seagate Technology LLCInventors: Jeffrey John Pream, Ara Patapoutian