Abstract: The present invention provides for dynamically determining a ratio of forwarded packets to injected packets to be transmitted in a bus ring. At least one forwarded packet is received into a first queue. An injected packet is received into a second queue. A determination, or snapshot, of the number of forwarded packets in the first queue due to the presence of the injected packet in the second queue is triggered. Packets corresponding to the snapshot are transmitted. After the packets are transmitted, if there is another injected packet stored in the second queue, another snapshot is performed. Packets corresponding to this snapshot are transmitted, and so on.

Abstract: A hardware emulator chip contains an array of cells and a programmable interconnection array. Each cell performs only a single logic function, which is configurable. The chips run asynchronously to one another, and within each chip cells are enabled by a sequential wave signal, which enables successive logical rows of cells. Within the chip, it is possible to connect any arbitrary cell output to any arbitrary cell input. Preferably, a set of off-chip connections is made possible by time-multiplexing the output of each subset to the wave signal. In one embodiment, full interconnection of cells within a chip is provided by providing a time-multiplexed programmable array of interconnect switches, the setting of each switch changing with each successive wave. In a second embodiment, full interconnection of cells within a chip is provided by providing a programmable array of interconnect switches.

Abstract: A hardware design emulation system that includes one or more emulators and one or more associated run-time assist units (RTAUs). The emulator logic is a combination of user model logic, reflecting the hardware design, and non-user model logic. A handshaking controller produces a domain step signal and a model step signal. The domain step signal indicates that the emulator is entering a state for executing the next step of the logic with which it is programmed, be it user model logic or non-user model logic. The model step signal indicates that the emulator is entering a state for advancing the user model defined by the user model logic. This dual handshaking protocol enhances versatility by enabling a wide variety of RTAUs to be used, particularly in combination with one another.

Abstract: The present invention provides for an integrated circuit (IC) bus system. A local IC is coupled to a remote IC through a bus interface. A local memory is coupled to the local IC. A bus interface controller is employable to track data transfer requests from the remote IC for data address that are contained within at least one segment of the first partitioned memory range. The bus interface controller is further employable to stop the forwarding of a data transfer request generated within the local IC to the remote IC, if the memory segment count corresponding to the data address of the locally generated data transfer request equals zero.

Abstract: An optical transmission bypass device attaching a network device to a fiber optic network allows fiber optic transmissions to bypass the network device when not powered, thereby maintaining continuity of the fiber network. A first and second actuating optical reflector has a reflective face that, in an un-powered state, is disposed to place the reflective face of the actuating optical reflector in a first position with respect to an optical path of an optical port, and, in a powered state, is disposed to place the reflective face of the actuating optical reflector in a second position with respect to the optical path of the optical port.

Abstract: An optical transmission bypass device attaching a network device to a fiber optic network allows fiber optic transmissions to bypass the network device when not powered, thereby maintaining continuity of the fiber network. A first and second actuating optical reflector has a reflective face that, in an un-powered state, is disposed to place the reflective face of the actuating optical reflector in a first position with respect to an optical path of an optical port, and, in a powered state, is disposed to place the reflective face of the actuating optical reflector in a second position with respect to the optical path of the optical port.

Abstract: A method partitions a netlist into multiple clock domains. The number of clock domains is the number of primary input clocks plus one freerun domain. First, each functional block in the netlist is colored with a number of colors corresponding to the number of primary input clocks. Buckets are then created, with one bucket corresponding to a particular clock domain. Each functional block in the netlist is then placed in one of the buckets according to one or more partition criterion, which takes into account the color of logic that feeds a functional block and the color of logic that the functional block feeds. The result is that the original netlist is partitioned into multiple netlists, each of which corresponds to a single clock domain. These multiple netlists may be executed in parallel to emulate the function of the circuit represented in the netlist.

Abstract: An apparatus and method utilize a buffer interposed in a common signal path between asynchronous clock domains in a hardware-based logic emulation environment to manage the communication of time-multiplexed data signals between the clock domains during hardware-based emulation. The buffer is effectively used to latch each data signal communicated across the common signal path so that the clock domain that receives the signals can retrieve each such signal at appropriate points in the receiver clock domain's evaluation cycle. Independently-controlled write/read pointers are maintained in a buffer control circuit to independently address the buffer for the transmitter and receiver sides of an asynchronous communication path.

Abstract: In accordance with the present invention, a system for providing high-speed sequential modeling in a simulator or emulator environment is provided. The system includes a sequential control system (microprocessor board) which is attached directly to an emulator. The sequential control system cycles or operates at a higher speed than the emulator. This allows the sequential control system to execute multiple commands during each hardware emulation cycle so that the concurrent operations model within the accelerator/emulator and the sequential operations model within the sequential control system achieve a high degree of parallel operation, greatly enhancing system speed and performance. Further, the system includes direct high-speed connections between the sequential control system and the host workstation so that the control system can be programmed to execute a sequential model and/or to exchange data directly with the host without actually passing any information through the hardware emulator/accelerator.