Abstract: Circuits, methods, and apparatus that provide differential-input, single-slope, column-parallel analog-to-digital converter (ADC) architectures for use in high-resolution CMOS image sensors (CIS) are described. A column ADC is coupled with a column of a pixel array and configured to convert a pixel signal level to a corresponding digital output value according to a ramp generator output. Each pixel is configured to output a pixel reset level and a pixel signal level at different operating stages, and the ramp generator output includes a ramp reset level and a ramp signal level at the same or different at different operating stages. The pixel and ramp outputs are used to differentially drive a comparator stage of the column ADC, for example, to reduce power supply noise.

Abstract: Circuits, methods, and apparatus are described that provide calibration of column-parallel analog-to-digital converters (ADCs) in image processing contexts only once per frame (or less frequently) to reduce column-wise noise. For example, the column ADCs are calibrated during an inter-frame time interval, like a vertical blanking interval. In some embodiments, calibration data for the column ADCs for a calibration period is stored at the digital block for use in processing row data from the column ADCs. In other embodiments, calibration data for the column ADCs for the calibration period is stored at column ADCs in a local memory for local correction of the pixel data prior to being read out to the digital block for processing. In certain embodiments, techniques, such as differential ADC architectures, are used to mitigate row-wise noise in context of the frame-wise calibration.

Abstract: Circuits, methods, and apparatus are described that provide calibration of column-parallel analog-to-digital converters (ADCs) in image processing contexts only once per frame (or less frequently) to reduce column-wise noise. For example, the column ADCs are calibrated during an inter-frame time interval, like a vertical blanking interval. In some embodiments, calibration data for the column ADCs for a calibration period is stored at the digital block for use in processing row data from the column ADCs. In other embodiments, calibration data for the column ADCs for the calibration period is stored at column ADCs in a local memory for local correction of the pixel data prior to being read out to the digital block for processing. In certain embodiments, techniques, such as differential ADC architectures, are used to mitigate row-wise noise in context of the frame-wise calibration.

Abstract: Circuits, methods, and apparatus that provide differential-input, single-slope, column-parallel analog-to-digital converter (ADC) architectures for use in high-resolution CMOS image sensors (CIS) are described. A column ADC is coupled with a column of a pixel array and configured to convert a pixel signal level to a corresponding digital output value according to a ramp generator output. Each pixel is configured to output a pixel reset level and a pixel signal level at different operating stages, and the ramp generator output includes a ramp reset level and a ramp signal level at the same or different at different operating stages. The pixel and ramp outputs are used to differentially drive a comparator stage of the column ADC, for example, to reduce power supply noise.