Abstract: A bidirectional bus circuit according to the present invention typically includes: (a) a first and a second bus line portion for carrying a bidirectional bus signal, where the first bus line portion has a first and a second end, and the second bus line portion has a third and a fourth end; (b) a bus direction sense line for carrying a bus direction signal; (c) a sensing circuit coupled to the sense line for detecting the bus direction signal; and (d) a driving circuit coupled to the sensing circuit and coupled between the second end of the first bus line portion and the third end of the second bus line portion for driving the first and second bus line portions. According to one embodiment of the present invention, the sensing circuit may include a cross coupled NAND gate latch or a cross coupled NOR gate latch. The driving circuit may include a first buffer circuit for driving the first bus line portion and a second buffer circuit for driving the second bus line portion.

Abstract: A memory cell with vertically stacked crossovers. In prior memory cells, crossover connections within the memory cell were implemented in the same device layer. This wasted valuable design space, since the crossovers were therefore required to sit side-by-side in the layout design. The present invention implements crossovers in different materials on different device layers. The crossovers may therefore be vertically stacked on top of each other, reducing the area of the memory cell.

Abstract: A method and an apparatus for providing an integrated circuit memory with redundancy. In one embodiment, an integrated circuit memory is organized into subarrays of rows and columns of memory cells. Each of the subarrays are sequentially grouped such that each subarray is adjacent to at least one other subarray. Included in the sequentially organized subarrays is a redundant subarray. Each subarray, including the redundant subarray, is configured to store data designated to be stored in a neighboring adjacent subarray. Therefore, if a defective memory cell is detected in any of the subarrays, the adjacent neighboring subarrays are configured to store the data designated for a neighboring subarray. As a result, the storage of data in the memory is shuffled towards the redundant subarray to implement redundancy.

Abstract: A PLL based deskewed clock generator which may be fully integrated on a microprocessor is disclosed. The clock generator has a skew of less than 0.1 ns with peak to peak jitter of 0.3 ns using a 0.8 .mu.m CMOS technology. The PLL comprises a phase frequency detector, charge pump, loop filter and voltage controlled oscillator from which the internal clock is generated. Since the PLL is on the same chip as the microprocessor, it is difficult to isolate the PLL from the noise generated by the microprocessor core logic and output buffers. Without an external filter, noise from the motherboard also influences the PLL. Power supply noise can cause a direct change in the frequency of the voltage controlled oscillator of the PLL. Circuits which overcome the adverse effects which would be created by such noises are also described.

Abstract: A BiCMOS circuit for amplifying the difference voltage between two input voltage signals. The BiCMOS circuit of the present invention includes two bipolar junction transistor which receive the two input voltage signals and each drive a cascode-connected PMOS device. The drains of the cascode-connected PMOS devices are coupled to the input and output of a current mirror, wherein the output of the current mirror is the output of the BiCMOS circuit.

Abstract: An MOS voltage-controlled resistor is disclosed. The voltage-controlled resistor comprises a first triode MOSFET, a second triode MOSFET, and a single diode connected MOSFET. The single diode connected MOSFET is coupled in series with the first triode MOSFET. These two MOSFETs in series, are in turn, coupled in parallel with the second triode MOSFET. A control voltage, V.sub.CONTROL, is applied from the gates to the sources of the first and second triode MOSFETs. A voltage-controlled resistance can then be measured between the two nodes defining the parallel coupling of, the single diode connected MOSFET in series with the first triode MOSFET, with the second triode MOSFET.

Abstract: A BiCMOS logic circuit which implements single stage inverting and non-inverting logic functions is described. The circuit includes pull-up and pull-down assembly means coupled between the input and the non-inverting output nodes. The pull-down assembly means comprises a pair of complimentary metal-oxide semiconductor field-effect transistors connected in an inverter configuration in which the gates of the pair of CMOS transistors are coupled to the input node while the output of the inverter configuration provides the inverting output while driving the gate of a n-channel transistor coupled between the non-inverting output node and V.sub.ss.

Abstract: A BiCMOS logic circuit which implements single stage noninverting logic functions is described. The circuit includes pull-up and pull-down assembly means coupled between the input and output nodes. The pull-down assembly means comprises a pair of complementary metal-oxide semiconductor field-effect transistors connected in an inverter configuration in which the gates of the pair of CMOS transistors are coupled to the input node while the output of the inverter configuration drives the base of a bipolar transistor coupled to the output node.

Abstract: A BiCMOS logic circuit which implements single stage noninverting logic functions is described. The circuit includes pull-up and pull-down assembly means coupled between the input and output nodes. The pull-down assemby means comprises a pair of complimentary metal-oxide semiconductor field-effect transistors connected in an inverter configuration in which the gates of the pair of CMOS transistors are coupled to the input node while the output of the inverter configuration drives the base of a bipolar transistor coupled to the output node.