Abstract: Example implementations relate to safe peripheral device communications. In one example, a host computing device can include a serializer/deserializer (SERDES), a PCIe bus, a video source, a connector coupled, via the SERDES, to the PCIe bus and the video source; and a host controller to operate in a safe mode and cause PCIe data from PCIe bus to be provided, via the SERDES and the connector, solely to a peripheral controller of a peripheral device.

Abstract: Examples relate to operating mode configuration. An apparatus may include a memory resource storing executable instructions. Instructions may include instructions to receive a message from a host computing device coupled to the apparatus. The message may include a Host Based Media Access Control Address (HBMA). Instructions may further include instructions to configure the apparatus using the HBMA in response to a determination that the apparatus is in a particular operating mode. The apparatus may further include a processing resource to execute the instructions stored on the memory resource.

Abstract: Examples relate to configuration parameter transfer. An apparatus may include a memory resource storing executable instructions. Instructions may include instructions to receive a first signal from a host computing device. Instructions may further include instructions to initiate communications with the host computing device in response to receiving the first signal. Instructions may further include instructions to receive a configuration parameter from the host computing device in response to initiation of communications with the host computing device. The apparatus may further include a processing resource to execute the instructions stored on the memory resource.

Abstract: Examples relate to operating mode configuration. An apparatus may include a memory resource storing executable instructions. Instructions may include instructions to receive a message from a host computing device coupled to the apparatus. The message may include a Host Based Media Access Control Address (HBMA). Instructions may further include instructions to configure the apparatus using the HBMA in response to a determination that the apparatus is in a particular operating mode. The apparatus may further include a processing resource to execute the instructions stored on the memory resource.

Abstract: Example implementations relate to safe peripheral device communications. In one example, a host computing device can include a serializer/deserializer (SERDES), a PCIe bus, a video source, a connector coupled, via the SERDES, to the PCIe bus and the video source; and a host controller to operate in a safe mode and cause PCIe data from PCIe bus to be provided, via the SERDES and the connector, solely to a peripheral controller of a peripheral device.

Abstract: Examples relate to configuration parameter transfer. An apparatus may include a memory resource storing executable instructions. Instructions may include instructions to receive a first signal from a host computing device. Instructions may further include instructions to initiate communications with the host computing device in response to receiving the first signal. Instructions may further include instructions to receive a configuration parameter from the host computing device in response to initiation of communications with the host computing device. The apparatus may further include a processing resource to execute the instructions stored on the memory resource.

Abstract: In one example, a system for a system management mode (SMM) privilege architecture includes a computing device comprising: a first portion of SMM instructions to set up a number of resources and implement a privilege architecture for the SMM of a computing device and a second portion of SMM instructions to execute a number of functions during the SMM of the computing device, wherein the privilege architecture assigns the first portion of SMM instructions to a first privilege level and assigns the second portion of SMM instructions to a second privilege level.

Abstract: A system in accordance with an example includes a communication module and an embedded controller. The communications module is to connect to a server. The embedded controller is to communicate with the server to receive a command and to initiate a power state transition of the system in response to the command.

Abstract: Example implementations relate to key revocation. For example, a system for key revocation may comprise a processor, an embedded controller, a non-volatile memory storing a system instruction signing key authorization data element, wherein the data element includes a system instruction signing key, a signing key number and a signature. The embedded controller may include a plurality of keys to verify the data element, and a one-time programmable (OTP) memory and a key among the plurality of keys that is revocable using the OTP memory, wherein revocation of the key permanently prevents the embedded controller from utilizing the key.

Abstract: In one example, a system for a system management mode (SMM) privilege architecture includes a computing device comprising: a first portion of SMM instructions to set up a number of resources and implement a privilege architecture for the SMM of a computing device and a second portion of SMM instructions to execute a number of functions during the SMM of the computing device, wherein the privilege architecture assigns the first portion of SMM instructions to a first privilege level and assigns the second portion of SMM instructions to a second privilege level.

Abstract: In one example, a system for a platform key hierarchy includes an embedded controller to, store a first public platform key with a key bit list corresponding to a number of valid private platform keys, and verify a second public platform key by comparing a key number corresponding to a private platform key to the key bit list.

Abstract: Example implementations relate to runtime verification. In one example, runtime verification includes a processor, a shared memory storing embedded controller instructions, and an embedded controller to verify the embedded controller instructions stored in the shared memory during runtime of the processor.

Abstract: In one example, a system for a platform key hierarchy includes an embedded controller to, store a first public platform key with a key bit list corresponding to a number of valid private platform keys, and verify a second public platform key by comparing a key number corresponding to a private platform key to the key bit list.

Abstract: Example implementations relate to key revocation. For example, a system for key revocation may comprise a processor, an embedded controller, a non-volatile memory storing a system instruction signing key authorization data element, wherein the data element includes a system instruction signing key, a signing key number and a signature. The embedded controller may include a plurality of keys to verify the data element, and a one-time programmable (OTP) memory and a key among the plurality of keys that is revocable using the OTP memory, wherein revocation of the key permanently prevents the embedded controller from utilizing the key.

Abstract: A system in accordance with an example includes a communication module and an embedded controller. The communications module is to connect to a server. The embedded controller is to communicate with the server to receive a command and to initiate a power state transition of the system in response to the command.

Abstract: Example implementations relate to runtime verification. In one example, runtime verification includes a processor, a shared memory storing embedded controller instructions, and an embedded controller to verify the embedded controller instructions stored in the shared memory during runtime of the processor.

Abstract: A system comprises an energy source that provides a system current for the system. The system also comprises logic coupled to the energy source. The logic receives an analog signal that is derived from a measurement of current in the system and computes an amount of energy consumed by the system based on the analog signal.

Abstract: A system comprises an energy source that provides a system current for the system. The system also comprises logic coupled to the energy source. The logic receives an analog signal that is derived from a measurement of current in the system and computes an amount of energy consumed by the system based on the analog signal.

Abstract: Apparatus and methods are provided for use with smart utility grids. A smart power supply includes power metering to determine instantaneous and cumulative energy consumption of the power supply and a computer coupled thereto. Communications transceivers enable the smart power supply to communicate with both the computer and smart entities of a smart utility grid. A user of the computer can view energy consumption data, utility rates, utility loading and other energy-related information by way of the smart power supply.

Abstract: A system comprises a sensor and logic coupled to the sensor. The logic programs a sensitivity level into the sensor to a first sensitivity level if a proxy indicates that the system is in transit and to a second sensitivity level if proxy indicates that the system is not in transit.