Abstract: Methods and structure for correlating multiple sets of test output signals in time are provided. The structure includes an integrated circuit comprising a block of circuitry that generates internal operational signals. The circuit also comprises a test multiplexer (MUX) hierarchy that selects subsets of the internal signals and applies the subsets to a testing element. A clock generator generates a clock signal for the selected signals. A test logic timer receives the clock signal and increments a counter value, and applies the counter value to the testing element. An event detector resets the counter value upon detection of an event, such that a first subset of the internal signals acquired from the test MUX hierarchy acquired responsive to detection of a first instance of the event may be correlated in time with a second subset of the internal signals acquired responsive to detection of a second instance of the event.

Abstract: Methods and structure are provided for routing internal operational signals of a circuit for output via an external interface. The structure includes an integrated circuit. The integrated circuit comprises a block of circuitry components operable to generate internal operational signals for performing designated functions during normal operation of the circuit, a control unit, a test signal routing hierarchy, and an external interface. The test signal routing hierarchy is coupled to receive the internal operational signals and controllably selects the internal operational signals for acquisition and applies them to the control unit. The external interface provides communications between the integrated circuit and an external device during normal operation of the integrated circuit.

Abstract: Methods and structure for correlating internal operational signals routed via different paths of a test signal selection hierarchy. The structure includes a functional block of circuitry operable to generate internal operational signals and clock signals. The integrated circuit also comprises a test signal selection hierarchy operable to receive the internal operational signals and the clock signals and to selectively route the internal operational signals and the clock signals. Further, structure includes a control unit operable to receive the clock signals from the test signal selection hierarchy, to determine a delay between received clock signals routed via different signaling pathways of the test signal selection hierarchy. The control unit is further operable to program a delay line based upon the delay between the clock signals and based upon internal operational signals correlated with the clock signals.

Abstract: Methods and structure for providing methods and structure for recovering errors in a hardware controller after an overwrite event, such as the detection of another error. In this regard, a link layer of the hardware controller is configured with a register that persistently stores errors until a processor can address them. The link layer is adapted to establish a connection between an initiator and a target and detect errors associated with the connection. As each detected error is overwritten by a subsequently detected error, the link layer register persistently stores the detected errors associated with the connection for recovery after the detected error has been overwritten in the link layer at least until the error can be handled.

Abstract: Methods and structure are provided for routing internal operational signals of a circuit for output via an external interface. The structure includes an integrated circuit. The integrated circuit comprises a block of circuitry components operable to generate internal operational signals for performing designated functions during normal operation of the circuit, a control unit, a test signal routing hierarchy, and an external interface. The test signal routing hierarchy is coupled to receive the internal operational signals and controllably selects the internal operational signals for acquisition and applies them to the control unit. The external interface provides communications between the integrated circuit and an external device during normal operation of the integrated circuit.

Abstract: Methods and structure for correlating multiple sets of test output signals in time are provided. The structure includes an integrated circuit comprising a block of circuitry that generates internal operational signals. The circuit also comprises a test multiplexer (MUX) hierarchy that selects subsets of the internal signals and applies the subsets to a testing element. A clock generator generates a clock signal for the selected signals. A test logic timer receives the clock signal and increments a counter value, and applies the counter value to the testing element. An event detector resets the counter value upon detection of an event, such that a first subset of the internal signals acquired from the test MUX hierarchy acquired responsive to detection of a first instance of the event may be correlated in time with a second subset of the internal signals acquired responsive to detection of a second instance of the event.

Abstract: Methods and structure for correlating internal operational signals routed via different paths of a test signal selection hierarchy. The structure includes a functional block of circuitry operable to generate internal operational signals and clock signals. The integrated circuit also comprises a test signal selection hierarchy operable to receive the internal operational signals and the clock signals and to selectively route the internal operational signals and the clock signals. Further, structure includes a control unit operable to receive the clock signals from the test signal selection hierarchy, to determine a delay between received clock signals routed via different signaling pathways of the test signal selection hierarchy. The control unit is further operable to program a delay line based upon the delay between the clock signals and based upon internal operational signals correlated with the clock signals.

Abstract: A method for detecting a failure in a serial topology. The method may comprise sending a predetermined pattern to a plurality of devices communicatively connected to an initiator in a serial topology; receiving a return result from each of the plurality of devices in response to the predetermined pattern; recognizing a problem associated with a particular device among the plurality of devices, the problem being recognized based on the return result from the particular device; sending a plurality of test patterns to the particular device; receiving a plurality of test results from the particular device in response to the plurality of test patterns; and determining a cause of the problem based on the plurality of test results, the cause of the problem being at least one of: a cable failure and a device failure.

Abstract: Methods and structure for providing methods and structure for recovering errors in a hardware controller after an overwrite event, such as the detection of another error. In this regard, a link layer of the hardware controller is configured with a register that persistently stores errors until a processor can address them. The link layer is adapted to establish a connection between an initiator and a target and detect errors associated with the connection. As each detected error is overwritten by a subsequently detected error, the link layer register persistently stores the detected errors associated with the connection for recovery after the detected error has been overwritten in the link layer at least until the error can be handled.

Abstract: An adapter card for testing the functionality of a particular interface configuration may include an interface core. The interface core may comprise an electric circuit including electronic components and control logic for interfacing with an information handling system device. The adapter card may include a front end data channel coupled with the interface core for transmitting data between the electronic components and the information handling system device. The adapter card may include firmware for setting an indicator and causing the control logic to report a memory requirement to the information handling system device larger than a programmed memory space expected by the control logic.

Abstract: A method for detecting a failure in a serial topology. The method may comprise sending a predetermined pattern to a plurality of devices communicatively connected to an initiator in a serial topology; receiving a return result from each of the plurality of devices in response to the predetermined pattern; recognizing a problem associated with a particular device among the plurality of devices, the problem being recognized based on the return result from the particular device; sending a plurality of test patterns to the particular device; receiving a plurality of test results from the particular device in response to the plurality of test patterns; and determining a cause of the problem based on the plurality of test results, the cause of the problem being at least one of: a cable failure and a device failure.

Abstract: Apparatus and methods for translation of data formats between multiple interface types. Translation logic is interposed between a producer circuit and a consumer circuit to translate data formats of data signals generated by the producer for application to the consumer. The translation logic may include multiple translators to provide translations between any of multiple producer data formats and any of multiple consumer data formats. One or more producer circuits may thus be selectively coupled with one or more consumer circuits through the translation logic circuit.

Abstract: Disclosed is a store and forward device that reduces latency. The store and forward device allows front end devices having various transfer protocols to be connected in a single path through a RAM, while reducing latency. Front end devices that transfer data on a piecemeal basis are required to transfer all of the data to a RAM prior to downloading data to a back end. Front end devices that transfer data in a single download begin the transfer of data out of a RAM as soon as a threshold value is reached. Hence, the latency associated with downloading all of the data into a RAM 118 and then transferring all of the data out of the RAM is eliminated.

Abstract: Apparatus methods for capturing flow control errors in FIFO exchanges between producing and consuming circuits operating in different clock domains. Tag information at the start of an exchange is transferred to a synchronizing component before data of a transfer transaction is entered in the FIFO. The tag information is also associated with each unit of data transferred to the FIFO by the producing circuit. The synchronizing component verifies the each unit of data retrieved by the consuming circuit has the expected tag information associated therewith and signals an error is the tag information does not match. Thus an error by the producing circuit in entering too much or too little data for a transfer is detected before erroneous data is retrieved and processed by the consuming circuit.

Abstract: Disclosed is a FIFO peek access device that utilizes a peek signal to access data stored in a FIFO without losing or erasing data. The peek signal is applied to read address logic and prevents the incrementing of the pointers in the peek address logic, so that after a read enable signal is asserted, the same data block can be accessed again on the next read enable signal.

Abstract: A method of eliminating a runaway condition in a PLL includes the steps of: determining whether the PLL is locked to an input reference signal; when the PLL is not locked to the input reference signal, determining whether a frequency of an output signal generated by the PLL exceeds a prescribed maximum frequency; and when the frequency of the output signal generated by the PLL exceeds the prescribed maximum frequency, resetting the PLL to thereby eliminate the runaway condition.

Abstract: A method of eliminating a runaway condition in a PLL includes the steps of: determining whether the PLL is locked to an input reference signal; when the PLL is not locked to the input reference signal, determining whether a frequency of an output signal generated by the PLL exceeds a prescribed maximum frequency; and when the frequency of the output signal generated by the PLL exceeds the prescribed maximum frequency, resetting the PLL to thereby eliminate the runaway condition.

Abstract: Apparatus methods for capturing flow control errors in FIFO exchanges between producing and consuming circuits operating in different clock domains. Tag information at the start of an exchange is transferred to a synchronizing component before data of a transfer transaction is entered in the FIFO. The tag information is also associated with each unit of data transferred to the FIFO by the producing circuit. The synchronizing component verifies the each unit of data retrieved by the consuming circuit has the expected tag information associated therewith and signals an error is the tag information does not match. Thus an error by the producing circuit in entering too much or too little data for a transfer is detected before erroneous data is retrieved and processed by the consuming circuit.

Abstract: Apparatus and methods for translation of data formats between multiple interface types. Translation logic is interposed between a producer circuit and a consumer circuit to translate data formats of data signals generated by the producer for application to the consumer. The translation logic may include multiple translators to provide translations between any of multiple producer data formats and any of multiple consumer data formats. One or more producer circuits may thus be selectively coupled with one or more consumer circuits through the translation logic circuit.

Abstract: Disclosed is a system that generates a write count value for indicating whether data can be read from a FIFO and a system that generates a read count value for indicating whether data can be written to a FIFO. Each of these systems operates in two separate clock domains. In the system that generates a write count value, write strobes are stored in parallel in a register in a first clock domain. The plurality of synchronizers trigger on a rising edge of the write strobe that is stored in the parallel register and generate an increment pulse in a second clock domain. An up/down counter reads the increment pulse in parallel and increments the up/down counter in parallel. A decrement signal from a read strobe decrements the up/down counter. The output of the counter is fed to a register that provides a write counter value to handshake logic that indicates whether data can be read from a FIFO without underflowing the FIFO.