Patents by Inventor Jeffrey Kehl

Jeffrey Kehl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9086976
    Abstract: A system and method of tracking multiple non-identification tagged requests in a system with multiple responders are disclosed. In one embodiment, an electronic memory system comprises a memory configured to implement a plurality of response queues, wherein one response queue is associated with one responder from a plurality of responders, and wherein a responder is a device capable of resolving the memory request. A tracking module is configured to assign identification information to a memory request that is received and store the identification information in one or more queues of the plurality of response queues; and to transmit the memory request to each responder that is associated with the one or more queues. A response module is configured to associate the identification information in the one or more queues with a response upon receiving the response from the one or more responders.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: July 21, 2015
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: R. Frank O'Bleness, Sujat Jamil, David E. Miner, Tom Hameenanttila, Jeffrey Kehl, Richard Bryant, Kim Schuttenberg
  • Patent number: 9058272
    Abstract: An apparatus including a snoop filter decoupled from a cache and an associated method for snoop filtering are disclosed. The snoop filter is decoupled from the cache such that the cache changes states of lines in the cache from a first state that is a clean state, such as an exclusive (E) state, to a second state that is not a clean state, such as a modified (M) state, without the snoop filter's knowledge. The snoop filter buffers addresses of replaced lines that are unknown to be clean until a write-back associated with the replacement lines occurs, or until actual states of the replaced lines are determined by the snoop filter generating a snoop. A multi-level cache system in which a reallocation or replacement policy is biased to favor replacing certain lines such as inclusive lines, non-temporal lines or prefetched lines that have not been accessed, is also disclosed.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: June 16, 2015
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Frank O'Bleness, Sujat Jamil, David Miner, Joseph Delgross, Tom Hameenanttila, Jeffrey Kehl, Adi Habusha
  • Patent number: 8688919
    Abstract: A system and method of tracking multiple non-identification tagged requests in a system with multiple responders using one or more tracking queues. In some embodiments, the system and method may be implemented in a snoop filter covering multiple caches. In some embodiments, a data-less bus query may be used to update the status of a requested line.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: April 1, 2014
    Assignee: Marvell International Ltd.
    Inventors: R. Frank O'Bleness, Sujat Jamil, David E. Miner, Tom Hameenanttila, Jeffrey Kehl, Richard Bryant, Kim Schuttenberg
  • Patent number: 8296525
    Abstract: A system and method of tracking multiple non-identification tagged requests in a system with multiple responders using one or more tracking queues. In some embodiments, the system and method may be implemented in a snoop filter covering multiple caches. In some embodiments, a data-less bus query may be used to update the status of a requested line.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: October 23, 2012
    Assignee: Marvell International Ltd.
    Inventors: Frank O'Bleness, Sujat Jamil, David E. Miner, Tom Hameenanttila, Jeffrey Kehl, Richard Bryant, Kim Schuttenberg
  • Patent number: 8135916
    Abstract: A processor includes a first level of cache memory and a first set of instructions configured to implement a first cache coherency protocol. The processor also includes a second set of instructions configured to implement a second cache coherency protocol and a cache coherency protocol selector having at least two choice-states. The processor further includes a cache coherency implementer configured to implement the first cache coherency protocol or the second cache coherency with respect to the first level of cache memory based on a selected choice-state of the cache coherency protocol selector.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: March 13, 2012
    Assignee: Marvell International Ltd.
    Inventors: R. Frank O'Bleness, Sujat Jamil, David E. Miner, Joseph Delgross, Tom Hameenanttila, Jeffrey Kehl