Patents by Inventor Jeffrey Kessenich

Jeffrey Kessenich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190287634
    Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a first voltage to the access line following a verify of the program operation then electrically floating the access line, connecting the access line to the first input of the operational amplifier, applying a second voltage to a second access line adjacent the access line, applying a reference current to the access line while applying the second voltage to the second access line, applying the reference voltage to the second input of the operational amplifier while applying the second voltage to the second access line, and indicating a fail status of the program operation if current flow to or from the access line exceeds the reference current sinking current from, or sourcing current to, respectively, the first access line.
    Type: Application
    Filed: June 5, 2019
    Publication date: September 19, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
  • Patent number: 10366767
    Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a particular voltage to an unselected access line of a program operation, sensing a current of a selected access line of the program operation while applying the particular voltage to the unselected access line, indicating a fail status of the program operation if an absolute value of the sensed current of the selected access line is greater than a particular current, and proceeding with the program operation if the absolute value of the sensed current of the selected access line is less than a particular current.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
  • Publication number: 20170352431
    Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a particular voltage to an unselected access line of a program operation, sensing a current of a selected access line of the program operation while applying the particular voltage to the unselected access line, indicating a fail status of the program operation if an absolute value of the sensed current of the selected access line is greater than a particular current, and proceeding with the program operation if the absolute value of the sensed current of the selected access line is less than a particular current.
    Type: Application
    Filed: August 25, 2017
    Publication date: December 7, 2017
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
  • Patent number: 9281078
    Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: March 8, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
  • Publication number: 20150364213
    Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 17, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
  • Patent number: 7952936
    Abstract: Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading the value from the one or more memory cells in read operations.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: May 31, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Andrei Mihnea, Todd Marquart, Jeffrey Kessenich
  • Publication number: 20100046303
    Abstract: Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading the value from the one or more memory cells in read operations.
    Type: Application
    Filed: October 27, 2009
    Publication date: February 25, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Andrei Mihnea, Todd Marquart, Jeffrey Kessenich
  • Patent number: 7619931
    Abstract: Methods and devices are disclosed, such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading value from one or more memory cells in read operations.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: November 17, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Andrei Mihnea, Todd Marquart, Jeffrey Kessenich
  • Publication number: 20090003078
    Abstract: Methods and devices are disclosed, such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading value from one or more memory cells in read operations.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 1, 2009
    Inventors: Andrei Mihnea, Todd Marquart, Jeffrey Kessenich
  • Publication number: 20070014158
    Abstract: A selected word line that is coupled to a cell to be programmed is biased during a program operation. The unselected word lines are biased with a negative potential to reduce the cell leakage at programming bit line potential. A programming pulse is applied to the bit line coupled to the cell to be programmed. During verification, the unselected word lines are biased back to ground potential.
    Type: Application
    Filed: September 18, 2006
    Publication date: January 18, 2007
    Inventor: Jeffrey Kessenich
  • Publication number: 20060146611
    Abstract: A selected wordline that is coupled to a cell to be programmed is biased during a program operation. The unselected wordlines are biased with a negative potential to reduce the cell leakage at programming bitline potential. A programming pulse is applied to the bitline coupled to the cell to be programmed. During verification, the unselected wordlines are biased back to ground potential.
    Type: Application
    Filed: March 3, 2006
    Publication date: July 6, 2006
    Inventor: Jeffrey Kessenich
  • Publication number: 20050248990
    Abstract: A selected wordline that is coupled to a cell to be programmed is biased during a program operation. The unselected wordlines are biased with a negative potential to reduce the cell leakage at programming bitline potential. A programming pulse is applied to the bitline coupled to the cell to be programmed. During verification, the unselected wordlines are biased back to ground potential.
    Type: Application
    Filed: May 7, 2004
    Publication date: November 10, 2005
    Inventor: Jeffrey Kessenich
  • Patent number: 6493280
    Abstract: A method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide is disclosed. The method uses an erase operation that over-erases all memory cells undergoing the erase operation. A cell healing operation is performed on the over-erased cells. The healing operation causes electrons to pass through the tunnel oxide and recombine with trapped holes. The recombination substantially reduces the trapped holes within the tunnel oxide without reducing the speed of the erase operation. Moreover, by reducing trapped holes, charge retention, overall performance and endurance of the flash memory cells are substantially increased.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: December 10, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Andrei Mihnea, Jeffrey Kessenich, Chun Chen
  • Publication number: 20020121653
    Abstract: A method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide is disclosed. The method uses an erase operation that over-erases all memory cells undergoing the erase operation. A cell healing operation is performed on the over-erased cells. The healing operation causes electrons to pass through the tunnel oxide and recombine with trapped holes. The recombination substantially reduces the trapped holes within the tunnel oxide without reducing the speed of the erase operation. Moreover, by reducing trapped holes, charge retention, overall performance and endurance of the flash memory cells are substantially increased.
    Type: Application
    Filed: October 22, 2001
    Publication date: September 5, 2002
    Inventors: Andrei Mihnea, Jeffrey Kessenich, Chun Chen
  • Patent number: 6426898
    Abstract: A method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide is disclosed. The method uses an erase operation that over-erases all memory cells undergoing the erase operation. A cell healing operation is performed on the over-erased cells. The healing operation causes electrons to pass through the tunnel oxide and recombine with trapped holes. The recombination substantially reduces the trapped holes within the tunnel oxide without reducing the speed of the erase operation. Moreover, by reducing trapped holes, charge retention, overall performance and endurance of the flash memory cells are substantially increased.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: July 30, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Andrei Mihnea, Jeffrey Kessenich, Chun Chen