Patents by Inventor Jeffrey Koelling
Jeffrey Koelling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11031405Abstract: Various embodiments comprise methods and related apparatuses formed from those methods for placing at least portions of peripheral circuits under a DRAM memory array, where the peripheral circuits are used to control an operation of the DRAM memory array. In an embodiment, a memory apparatus includes a DRAM memory array and at least one peripheral circuit formed under the DRAM memory array, where the at least one peripheral circuit includes at least one circuit type selected from sense amplifiers and sub-word line drivers. Additional apparatuses and methods are also disclosed.Type: GrantFiled: November 2, 2017Date of Patent: June 8, 2021Assignee: Micron Technology, Inc.Inventors: Mansour Fardad, Harish N. Venkata, Jeffrey Koelling
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Publication number: 20190131308Abstract: Various embodiments comprise methods and related apparatuses formed from those methods for placing at least portions of peripheral circuits under a DRAM memory array, where the peripheral circuits are used to control an operation of the DRAM memory array. In an embodiment, a memory apparatus includes a DRAM memory array and at least one peripheral circuit formed under the DRAM memory array, where the at least one peripheral circuit includes at least one circuit type selected from sense amplifiers and sub-word line drivers. Additional apparatuses and methods are also disclosed.Type: ApplicationFiled: November 2, 2017Publication date: May 2, 2019Inventors: Mansour Fardad, Harish N. Venkata, Jeffrey Koelling
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Publication number: 20070158695Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: ApplicationFiled: March 8, 2007Publication date: July 12, 2007Applicants: HITACHI, LTD., TEXAS INSTRUMENTS INCORPORATEDInventors: Goro KITSUKAWA, Takesada AKIBA, Hiroshi OTORI, William McKEE, Jeffrey KOELLING, Troy HERNDON
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Publication number: 20050237778Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: ApplicationFiled: June 22, 2005Publication date: October 27, 2005Applicants: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William McKee, Jeffrey Koelling, Troy Herndon
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Patent number: 6952371Abstract: A booting circuit, used during antifuse programming, that has a clamping circuit designed to prevent a programming voltage from being unnecessarily limited by other components in an integrated circuit. The booting circuit is connected between an external interface, such as a bond pad, and an internal line, and is activated when the programming voltage is being applied directly to the internal line (i.e., not through the external interface). When activated, the clamping circuit allows a suitable and sufficiently high voltage to be applied to the internal line to properly program the antifuses while also clamping the amount of voltage seen at the external interface.Type: GrantFiled: September 2, 2004Date of Patent: October 4, 2005Assignee: Micron Technology, Inc.Inventors: Jeffrey Koelling, Timothy B. Cowles
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Patent number: 6933769Abstract: A reference circuit generates a reference voltage from a supply voltage. The reference circuit includes a current generating unit for generating generated currents. An output unit of the reference circuit generates the reference voltage based on the generated currents. A startup unit of the reference circuit allows the reference voltage to switch between different voltages levels in different modes.Type: GrantFiled: August 26, 2003Date of Patent: August 23, 2005Assignee: Micron Technology, Inc.Inventor: Jeffrey Koelling
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Publication number: 20050046466Abstract: A reference circuit generates a reference voltage from a supply voltage. The reference circuit includes a current generating unit for generating generated currents. An output unit of the reference circuit generates the reference voltage based on the generated currents. A startup unit of the reference circuit allows the reference voltage to switch between different voltages levels in different modes.Type: ApplicationFiled: August 26, 2003Publication date: March 3, 2005Inventor: Jeffrey Koelling
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Publication number: 20050041481Abstract: A booting circuit, used during antifuse programming, that has a clamping circuit designed to prevent a programming voltage from being unnecessarily limited by other components in an integrated circuit. The booting circuit is connected between an external interface, such as a bond pad, and an internal line, and is activated when the programming voltage is being applied directly to the internal line (i.e., not through the external interface). When activated, the clamping circuit allows a suitable and sufficiently high voltage to be applied to the internal line to properly program the antifuses while also clamping the amount of voltage seen at the external interface.Type: ApplicationFiled: September 2, 2004Publication date: February 24, 2005Inventors: Jeffrey Koelling, Timothy Cowles
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Publication number: 20050035403Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: ApplicationFiled: September 20, 2004Publication date: February 17, 2005Applicants: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William McKee, Jeffrey Koelling, Troy Herndon
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Patent number: 6807113Abstract: A booting circuit, used during antifuse programming, that has a clamping circuit designed to prevent a programming voltage from being unnecessarily limited by other components in an integrated circuit. The booting circuit is connected between an external interface, such as a bond pad, and an internal line, and is activated when the programming voltage is being applied directly to the internal line (i.e., not through the external interface). When activated, the clamping circuit allows a suitable and sufficiently high voltage to be applied to the internal line to properly program the antifuses while also clamping the amount of voltage seen at the external interface.Type: GrantFiled: October 17, 2003Date of Patent: October 19, 2004Assignee: Micron Technology, Inc.Inventors: Jeffrey Koelling, Timothy B. Cowles
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Publication number: 20040136243Abstract: A booting circuit, used during antifuse programming, that has a clamping circuit designed to prevent a programming voltage from being unnecessarily limited by other components in an integrated circuit. The booting circuit is connected between an external interface, such as a bond pad, and an internal line, and is activated when the programming voltage is being applied directly to the internal line (i.e., not through the external interface). When activated, the clamping circuit allows a suitable and sufficiently high voltage to be applied to the internal line to properly program the antifuses while also clamping the amount of voltage seen at the external interface.Type: ApplicationFiled: October 17, 2003Publication date: July 15, 2004Inventors: Jeffrey Koelling, Timothy B. Cowles
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Patent number: 6657905Abstract: A booting circuit, used during antifuse programming, that has a clamping circuit designed to prevent a programming voltage from being unnecessarily limited by other components in an integrated circuit. The booting circuit is connected between an external interface, such as a bond pad, and an internal line, and is activated when the programming voltage is being applied directly to the internal line (i.e., not through the external interface). When activated, the clamping circuit allows a suitable and sufficiently high voltage to be applied to the internal line to properly program the antifuses while also clamping the amount of voltage seen at the external interface.Type: GrantFiled: May 17, 2002Date of Patent: December 2, 2003Assignee: Micron Technology, Inc.Inventors: Jeffrey Koelling, Timothy B. Cowles
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Publication number: 20030214846Abstract: A booting circuit, used during antifuse programming, that has a clamping circuit designed to prevent a programming voltage from being unnecessarily limited by other components in an integrated circuit. The booting circuit is connected between an external interface, such as a bond pad, and an internal line, and is activated when the programming voltage is being applied directly to the internal line (i.e., not through the external interface). When activated, the clamping circuit allows a suitable and sufficiently high voltage to be applied to the internal line to properly program the antifuses while also clamping the amount of voltage seen at the external interface.Type: ApplicationFiled: May 17, 2002Publication date: November 20, 2003Inventors: Jeffrey Koelling, Timothy B. Cowles
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Patent number: 5978254Abstract: A circuit is designed with a decoder circuit (10), responsive to a first input signal (81) having a first voltage range, for producing a first output signal. An output circuit (11), responsive to the first output signal, produces a second output signal (26) having a second voltage range. The second voltage range includes a voltage less than a least voltage of the first voltage range and a voltage greater than a greatest voltage of the first voltage range.Type: GrantFiled: February 20, 1998Date of Patent: November 2, 1999Assignee: Texas Instruments IncorporatedInventors: Hugh P. McAdams, Jeffrey Koelling
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Patent number: 5792682Abstract: A circuit is designed with a decoder circuit (10), responsive to a first input signal (81) having a first voltage range, for producing a first output signal. An output circuit (11), responsive to the first output signal, produces a second output signal (26) having a second voltage range. The second voltage range includes a voltage less than a least voltage of the first voltage range and a voltage greater than a greatest voltage of the first voltage range.Type: GrantFiled: April 23, 1997Date of Patent: August 11, 1998Assignee: Texas Instruments IncorporatedInventors: Hugh P. McAdams, Jeffrey Koelling
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Patent number: 5696721Abstract: A circuit is designed with a decoder circuit (10), responsive to a first input signal (81) having a first voltage range, for producing a first output signal. An output circuit (11), responsive to the first output signal, produces a second output signal (26) having a second voltage range. The second voltage range includes a voltage less than a least voltage of the first voltage range and a voltage greater than a greatest voltage of the first voltage range.Type: GrantFiled: May 5, 1995Date of Patent: December 9, 1997Assignee: Texas Instruments IncorporatedInventors: Hugh P. McAdams, Jeffrey Koelling