Patents by Inventor Jeffrey L. Burns
Jeffrey L. Burns has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240123891Abstract: A hoist system may be used to raise and mount an interchangeable vehicle body onto a vehicle chassis. The hoist system may include a hoist frame having a roller, a subframe, a pivotal connection between the hoist frame and the subframe, a hinge joint member interconnected between the hoist frame and the subframe and a winch assembly connected to the hoist system. The subframe may have a bolt-on assembly for selectively, fixedly connecting the subframe to the vehicle chassis and the winch assembly may be selectively operable to raise the interchangeable body onto the hoist frame as the interchangeable body engages the roller.Type: ApplicationFiled: December 22, 2023Publication date: April 18, 2024Inventors: Brian L. JARRETT, Andrew J. SCHUMACHER, Jeffrey M. BURNS
-
Patent number: 8271055Abstract: An interface transceiver power management method and apparatus including controlled circuit complexity and power supply voltage reduces power consumption when interface conditions will support a transceiver having reduced complexity. The power supply voltage of the reduced complexity logic is then reduced if the lowered complexity will support a lower power supply voltage. The reduced complexity in combination with a reduced power supply voltage decreases power consumption to a greater degree than reducing transceiver complexity alone. The complexity of processing blocks within the receiver and/or transmitter are adjusted in conformity with one or more selection signals and an operating voltage level is selected in accordance with the requirements of the reduced complexity circuit.Type: GrantFiled: November 21, 2002Date of Patent: September 18, 2012Assignee: International Business Machines CorporationInventors: Juan-Antonio Carballo, Jeffrey L. Burns
-
Patent number: 7443195Abstract: A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.Type: GrantFiled: February 9, 2004Date of Patent: October 28, 2008Assignee: International Business Machines CorporationInventors: Juan-Antonio Carballo, Jeffrey L. Burns, Gary Dale Carpenter, Kevin John Nowka, Ivan Vo, Seung-moon Yoo
-
Patent number: 7269397Abstract: A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.Type: GrantFiled: June 14, 2006Date of Patent: September 11, 2007Assignee: International Business Machines CorporationInventors: Juan-Antonio Carballo, Jeffrey L. Burns, Ivan Vo
-
Patent number: 7133654Abstract: A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.Type: GrantFiled: August 7, 2003Date of Patent: November 7, 2006Assignee: International Business Machines CorporationInventors: Juan-Antonio Carballo, Jeffrey L. Burns, Ivan Vo
-
Patent number: 6812739Abstract: A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.Type: GrantFiled: September 26, 2002Date of Patent: November 2, 2004Assignee: International Business Machines CorporationInventors: Juan-Antonio Carballo, Jeffrey L. Burns, Gary Dale Carpenter, Kevin John Nowka, Ivan Vo, Seung-moon Yoo
-
Publication number: 20040203477Abstract: An interface transceiver power management method and apparatus including controlled circuit complexity and power supply voltage reduces power consumption when interface conditions will support a transceiver having reduced complexity. The power supply voltage of the reduced complexity logic is then reduced if the lowered complexity will support a lower power supply voltage. The reduced complexity in combination with a reduced power supply voltage decreases power consumption to a greater degree than reducing transceiver complexity alone.Type: ApplicationFiled: November 21, 2002Publication date: October 14, 2004Applicant: International Business Machines CorporationInventors: Juan-Antonio Carballo, Jeffrey L. Burns
-
Publication number: 20040203483Abstract: An interlace transceiver power management method and apparatus reduces power consumption when interface conditions will support a transceiver having reduced complexity. Characteristics of the receiver and/or transmitter are adjusted in conformity with one or more selection signals. An interface quality measurement circuit may provide the selection signal, so that the transceiver complexity is adjusted in response to measured interface conditions or an external pin or register bit may be coupled to a select input. The receiver complexity adjustment may include the receiver sampling depth, window width, resolution or equalization complexity or other characteristic having an impact on receiver circuit power consumption. The transmitter complexity may be equalization, transmitter power or other characteristic having an impact on transmitter circuit power consumption.Type: ApplicationFiled: November 7, 2002Publication date: October 14, 2004Applicant: International Business Machines CorporationInventors: Juan-Antonio Carballo, David William Boerstler, Jeffrey L. Burns
-
Patent number: 6791361Abstract: A method and circuit for mitigating gate leakage during a sleep state. An input pattern may be applied to one or more of a plurality of devices in a circuit, e.g., static circuit, dynamic circuit, during a sleep state. In response to the application of the input pattern, a majority of the devices in the circuit may have a substantially identical voltage at each of its terminals, i.e., the source, gate and drain terminal, thereby mitigating gate leakage.Type: GrantFiled: December 12, 2002Date of Patent: September 14, 2004Assignee: International Business Machines CorporationInventors: Elad Alon, Jeffrey L. Burns, Kevin J. Nowka, Rahul M. Rao
-
Publication number: 20040157569Abstract: A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.Type: ApplicationFiled: February 9, 2004Publication date: August 12, 2004Inventors: Juan-Antonio Carballo, Jeffrey L. Burns, Gary Dale Carpenter, Kevin John Nowka, Ivan Vo, Seung-moon Yoo
-
Publication number: 20040113657Abstract: A method and circuit for mitigating gate leakage during a sleep state. An input pattern may be applied to one or more of a plurality of devices in a circuit, e.g., static circuit, dynamic circuit, during a sleep state. In response to the application of the input pattern, a majority of the devices in the circuit may have a substantially identical voltage at each of its terminals, i.e., the source, gate and drain terminal, thereby mitigating gate leakage.Type: ApplicationFiled: December 12, 2002Publication date: June 17, 2004Applicant: International Business Machines CorporationInventors: Elad Alon, Jeffrey L. Burns, Kevin J. Nowka, Rahul M. Rao
-
Patent number: 6724221Abstract: In one form of the invention, circuitry having exclusive-OR and latch functionality includes timing circuitry and logic circuitry. The circuitry includes a memory, with first and second memory nodes, for storing a state and its complement, and first and second timing circuitry portions, each operable to receive at least one timing signal, coupled to the respective memory nodes. The logic circuitry includes first and second logic circuitry portions, each of which is operable to receive at least first and second data signals. Each of the logic circuitry portions is coupled in series with a conditionally conductive path of one of the respective first and second timing circuitry portions.Type: GrantFiled: March 28, 2002Date of Patent: April 20, 2004Assignee: International Business Machines CorporationInventors: Juan-Antonio Carballo, David William Boerstler, Jeffrey L. Burns, Kevin John Nowka, Li Shi
-
Publication number: 20040061523Abstract: A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.Type: ApplicationFiled: September 26, 2002Publication date: April 1, 2004Applicant: International Business Machine CorporationInventors: Juan-Antonio Carballo, Jeffrey L. Burns, Gary Dale Carpenter, Kevin John Nowka, Ivan Vo, Seung-moon Yoo
-
Patent number: 6650163Abstract: A system and integrated circuit (die) including a clock generator that includes an on-chip inductor and uses the inherent capacitance of the load to generate a sinusoidal clock signal. The inductor is connected between a current source and an inverting switch. The output of the switch is a substantially sinusoidal signal that connected directly to at least a portion of the clock driven circuits without intermediate buffering. In the preferred embodiment, the clock generator is a dual phase design that includes a pair of cross-coupled MOSFET's, a pair of solid state on-chip inductors, and a current source. Each of the on-chip inductors is connected between the current source and the drain of one of the MOSFET's. The outputs of the clock generator are provided directly to the clock inputs of at least a portion of the clock driven circuits on the die.Type: GrantFiled: August 8, 2002Date of Patent: November 18, 2003Assignee: International Business Machines CorporationInventors: Jeffrey L. Burns, Alan James Drake, Uttam Shyamalindu Ghoshal, Kevin John Nowka
-
Publication number: 20030184340Abstract: In one form of the invention, circuitry having exclusive-OR and latch functionality includes timing circuitry and logic circuitry. The circuitry includes a memory, with first and second memory nodes, for storing a state and its complement, and first and second timing circuitry portions, each operable to receive at least one timing signal, coupled to the respective memory nodes. The logic circuitry includes first and second logic circuitry portions, each of which is operable to receive at least first and second data signals. Each of the logic circuitry portions is coupled in series with a conditionally conductive path of one of the respective first and second timing circuitry portions.Type: ApplicationFiled: March 28, 2002Publication date: October 2, 2003Applicant: International Business Machines CorporationInventors: Juan-Antonio Carballo, David William Boerstler, Jeffrey L. Burns, Kevin John Nowka, Li Shi
-
Patent number: 6621358Abstract: In a first form, a voltage controlled oscillator includes delay cells connected in a ring, and control elements connected to selectively bypass respective sets of the delay cells. The delay cells are operable to receive respective differential inputs and to generate inverted outputs. The control elements are operable to receive respective differential inputs and to generate non-inverted outputs with variable delays. The control element delays are variable responsive to respective differential control voltages.Type: GrantFiled: December 17, 2001Date of Patent: September 16, 2003Assignee: International Business Machines CorporationInventors: Juan-Antonio Carballo, David William Boerstler, Jeffrey L. Burns, Ivan Vo
-
Publication number: 20030112082Abstract: In a first form, a voltage controlled oscillator includes delay cells connected in a ring, and control elements connected to selectively bypass respective sets of the delay cells. The delay cells are operable to receive respective differential inputs and to generate inverted outputs. The control elements are operable to receive respective differential inputs and to generate non-inverted outputs with variable delays. The control element delays are variable responsive to respective differential control voltages.Type: ApplicationFiled: December 17, 2001Publication date: June 19, 2003Applicant: International Business Machines CorporationInventors: Juan-Antonio Carballo, David William Boerstler, Jeffrey L. Burns, Ivan Vo
-
Patent number: 6035390Abstract: A processor includes at least an execution unit that executes an instruction by performing an operation indicated by the instruction utilizing one or more operands and condition code logic that determines less than, greater than, and equal to condition code bits associated with the instruction concurrently with execution of the instruction by the execution unit. In one embodiment, the condition code logic includes a single computation stage that receives as inputs individual bit values of bit positions within first and second operands and logically combines the individual bit values. The single computation stage outputs, for each bit position, propagate, generate, and kill signals that collectively indicate values for the less than, greater than, and equal to condition code bits. One or more merging stages coupled to the computation stage then merge the propagate, generate, and kill signals into output signals that set the condition code bits.Type: GrantFiled: January 12, 1998Date of Patent: March 7, 2000Assignee: International Business Machines CorporationInventors: Jeffrey L. Burns, Sang Hoo Dhong, Kevin John Nowka, Joel Abraham Silberman