Abstract: An information handling system may include a host system comprising a host system processor and a management controller communicatively coupled to the host system processor and comprising a main processor for implementing functionality of the management controller and a co-processor communicatively coupled to the host system processor and configured to implement a proxy to the host system to enable the host system to access devices managed by the management controller.

Abstract: A system may include a controller, an endpoint device, and a cable coupled between the controller and the endpoint device and comprising a communication wire for bidirectionally communicating signals between the controller and the endpoint device and a circuit formed as a part of the cable and communicatively coupled to the communication wire, the circuit having a microcontroller unit configured to communicate identifying information regarding the cable to the controller via the communication wire and without contention with the signals bidirectionally communicated between the controller and the endpoint device.

Abstract: An information handling system may include an air mover configured to drive a flow of air and a processing component communicatively coupled to the air mover for controlling operation of the air mover via a first wire configured to communicate analog air mover speed commands from the processing component to the air mover for controlling a speed of the air mover and a second wire configured to communicate analog tachometer information from the air mover to the processing component. At least one of the air mover and the processing component may be configured to initiate a mode for serial digital communication via the first wire and the second wire. The air mover and the processing component may be configured to communicate information to each other in accordance with a digital communication protocol via the first wire and the second wire during the mode for serial digital communication.

Abstract: An information handling system may include an air mover configured to drive a flow of air and a processing component communicatively coupled to the air mover for controlling operation of the air mover via a first wire configured to communicate analog air mover speed commands from the processing component to the air mover for controlling a speed of the air mover and a second wire configured to communicate analog tachometer information from the air mover to the processing component. At least one of the air mover and the processing component may be configured to initiate a mode for serial digital communication via the first wire and the second wire. The air mover and the processing component may be configured to communicate information to each other in accordance with a digital communication protocol via the first wire and the second wire during the mode for serial digital communication.

Abstract: Systems and methods for staggering the release of multiple endpoints from a power brake event. A MCU on each riser implements a riser offset delay based on its position in an order in which power is to be released. For a riser with multiple slots, a delay circuit may be connected to one or more slots to provide a unique offset time to delay the release of power supply the slot. In some systems, a baseboard management controller (BMC) identifies endpoints subject to a power brake event during a POST process. Risers and slots that are not subject to a power brake event are identified and not included in the determination of delays or offset times.

Abstract: Systems and methods for staggering the release of multiple endpoints from a power brake event. A MCU on each riser implements a riser offset delay based on its position in an order in which power is to be released. For a riser with multiple slots, a delay circuit may be connected to one or more slots to provide a unique offset time to delay the release of power supply the slot. In some systems, a baseboard management controller (BMC) identifies endpoints subject to a power brake event during a POST process. Risers and slots that are not subject to a power brake event are identified and not included in the determination of delays or offset times.

Abstract: An information handling system may include a bus initiator, a plurality of bus endpoints, and a bus communicatively coupled between the bus initiator and the plurality of bus endpoints, wherein the bus comprises a multiplexer topology of a plurality of multiplexers. The bus initiator may be configured to perform in-band addressing to select a communications channel through the multiplexer topology via an addressing protocol that uses pulse bursts for initiation of the addressing, identification of the communications channel, and termination of the addressing. Pulses of the pulse bursts may be sufficiently short in duration to pass through filters of the bus endpoints such that the pulse bursts are not processed by the endpoints.

Abstract: An automated device discovery system includes a chassis defining device slots, with device connectors located adjacent each of the device slots. A bus subsystem and a reset subsystem are coupled to the device connectors. A processing system, which is coupled to each of the at least one bus system and the reset subsystem, causes the reset subsystem to sequentially assert reset instructions through each of the device connectors in a device slot sequence. The processing system then sequentially detects, via bus paths in the bus subsystem, each device that is located in one the device slots and coupled to its respective device connector based on reset operations performed by that device in response to the sequentially asserted reset instructions. The processing system then maps each device that was detected with a respective device slot identifier that corresponds to the device slot sequence in which the reset instructions were asserted.

Abstract: An automated device discovery system includes a chassis defining device slots, with device connectors located adjacent each of the device slots. A bus subsystem and a reset subsystem are coupled to the device connectors. A processing system, which is coupled to each of the at least one bus system and the reset subsystem, causes the reset subsystem to sequentially assert reset instructions through each of the device connectors in a device slot sequence. The processing system then sequentially detects, via bus paths in the bus subsystem, each device that is located in one the device slots and coupled to its respective device connector based on reset operations performed by that device in response to the sequentially asserted reset instructions. The processing system then maps each device that was detected with a respective device slot identifier that corresponds to the device slot sequence in which the reset instructions were asserted.

Abstract: An information handling system includes a planar board and a peripheral interface device. The planar board includes a central processing unit, a baseboard management controller, and an interface logic circuit. The peripheral interface device includes a microcontroller and a serial communication interface device. The peripheral interface device is coupled to a peripheral device. The information handling system also includes an interconnect to couple signals from the planar board to the peripheral interface device. The interconnect includes a single wire to couple first information from the interface logic circuit to the peripheral interface device and to couple second information from the serial communication interface device to the interface logic circuit. The first information includes a first power control command.

Abstract: An information handling system includes a data processor, a security co-processor, and a baseboard management controller (BMC). The security co-processor operates during a first in time portion of a boot process of the information handling system. The BMC provides first video display content during the first in time portion of the boot process. The data processor provides second video display content during a second in time portion of the boot process.

Abstract: An information handling system includes a DIMM including a SPD and a slave I2C interface, a processor complex including a first master I2C interface selectively coupled to the slave I2C interface during a system boot state, a BMC including a second master I2C interface selectively coupled to the slave I2C interface during a power-off state, and reset logic configured to select the first master I2C interface to be coupled to the slave I2C interface during the system boot state, select the second master I2C interface to be coupled to the slave I2C interface during the power-off state, detect a transition between the power-off state and the system boot state, and delay the selection of the first master I2C interface to be coupled to the slave I2C interface until the BMC is finished communicating with the SPD.

Abstract: An information handling system includes a processor complex and a microcontroller unit (MCU). The processor complex includes a Real-Time Clock (RTC) function associated with a port of the processor complex, and that can be invoked on the processor complex by a call to the port. The MCU includes RTC logic to maintain time base information for the information handling system. When the RTC function is invoked, the processor complex traps the call to the port and redirects the call to the MCU. When the MCU receives the redirected call, the MCU invokes the RTC logic to respond to the redirected call and to provide the time base information to the processor complex.

Abstract: An information handling system includes a DIMM including a SPD and a slave I2C interface, a processor complex including a first master I2C interface selectively coupled to the slave I2C interface during a system boot state, a BMC including a second master I2C interface selectively coupled to the slave I2C interface during a power-off state, and reset logic configured to select the first master I2C interface to be coupled to the slave I2C interface during the system boot state, select the second master I2C interface to be coupled to the slave I2C interface during the power-off state, detect a transition between the power-off state and the system boot state, and delay the selection of the first master I2C interface to be coupled to the slave I2C interface until the BMC is finished communicating with the SPD.

Abstract: An information handling system includes a processor complex and a microcontroller unit (MCU). The processor complex includes a Real-Time Clock (RTC) function associated with a port of the processor complex, and that can be invoked on the processor complex by a call to the port. The MCU includes RTC logic to maintain time base information for the information handling system. When the RTC function is invoked, the processor complex traps the call to the port and redirects the call to the MCU. When the MCU receives the redirected call, the MCU invokes the RTC logic to respond to the redirected call and to provide the time base information to the processor complex.

Abstract: An information handling system includes a data processor, a security co-processor, and a baseboard management controller (BMC). The security co-processor operates during a first in time portion of a boot process of the information handling system. The BMC provides first video display content during the first in time portion of the boot process. The data processor provides second video display content during a second in time portion of the boot process.

Abstract: A PXI Express controller may be configured to support at least three different conditions under which the controller may be turned on. If a chassis (e.g. a PXI Express chassis) interfacing with the controller has a power button, the first condition (which may be considered normal operation) may be met when the power button is being pressed at a time auxiliary power is present. When the chassis does not have a power button, the second condition may be met when the power is switched on at a time auxiliary power is present, and the third condition may be met when the power is switched on at a time auxiliary power is not present. A state-machine comprised in the PXI Express controller may be configured to interface with a chipset equally comprised in the PXI Express controller, to perform the control functions required to provide the support for the three different conditions.

Abstract: A PXI Express controller may be configured to support at least three different conditions under which the controller may be turned on. If a chassis (e.g. a PXI Express chassis) interfacing with the controller has a power button, the first condition (which may be considered normal operation) may be met when the power button is being pressed at a time auxiliary power is present. When the chassis does not have a power button, the second condition may be met when the power is switched on at a time auxiliary power is present, and the third condition may be met when the power is switched on at a time auxiliary power is not present. A state-machine comprised in the PXI Express controller may be configured to interface with a chipset equally comprised in the PXI Express controller, to perform the control functions required to provide the support for the three different conditions.

Abstract: A PXI Express controller may be configured to support at least three different conditions under which the controller may be turned on. If a chassis (e.g. a PXI Express chassis) interfacing with the controller has a power button, the first condition (which may be considered normal operation) may be met when the power button is being pressed at a time auxiliary power is present. When the chassis does not have a power button, the second condition may be met when the power is switched on at a time auxiliary power is present, and the third condition may be met when the power is switched on at a time auxiliary power is not present. A state-machine comprised in the PXI Express controller may be configured to interface with a chipset equally comprised in the PXI Express controller, to perform the control functions required to provide the support for the three different conditions.

Abstract: A PXI Express controller may be configured to support at least three different conditions under which the controller may be turned on. If a chassis (e.g. a PXI Express chassis) interfacing with the controller has a power button, the first condition (which may be considered normal operation) may be met when the power button is being pressed at a time auxiliary power is present. When the chassis does not have a power button, the second condition may be met when the power is switched on at a time auxiliary power is present, and the third condition may be met when the power is switched on at a time auxiliary power is not present. A state-machine comprised in the PXI Express controller may be configured to interface with a chipset equally comprised in the PXI Express controller, to perform the control functions required to provide the support for the three different conditions.