Abstract: A method of forming a semiconductor device includes forming, over a hardmask layer and an underlying layer of a substrate, a pattern of first trenches between adjacent template lines, each of the first trenches exposing a portion of the hardmask layer, and each of the template lines including a mandrel and spacers on sidewalls of the mandrel; forming a pattern of first blocks over the pattern of the first trenches and the template lines, the first blocks dividing the first trenches to form a pattern of first stencil trenches; transferring the pattern of first stencil trenches to the hardmask layer to form a pattern of first hardmask trenches, each of the first hardmask trenches exposing a portion of the underlying layer; forming a first fill layer filling the first hardmask trenches and exposing the mandrels; selectively removing the mandrels to form second trenches, each of the second trenches exposing a portion of the hardmask layer; and forming a conformal liner in the second trenches and over a surface of

Abstract: In accordance with an embodiment of the present invention, a resolver system has at least one resolver and at least one amplifier in electrical communication with each resolver. A reference circuit is in electrical communication with the amplifiers. The reference circuit provides reference signals to the amplifiers. A non-linearity calibration and compensation circuit in communication with each amplifier uses the amplified reference signals to provide scale factors, so as to enhance a precision of the resolver system.

Abstract: In accordance with an embodiment of the present invention, a resolver system has at least one resolver and at least one amplifier in electrical communication with each resolver. A reference circuit is in electrical communication with the amplifiers. The reference circuit provides reference signals to the amplifiers. A non-linearity calibration and compensation circuit in communication with each amplifier uses the amplified reference signals to provide scale factors, so as to enhance a precision of the resolver system.

Abstract: In accordance with an embodiment of the present invention, a resolver system has at least one resolver and at least one amplifier in electrical communication with each resolver. A reference circuit is in electrical communication with the amplifiers. The reference circuit provides reference signals to the amplifiers. A non-linearity calibration and compensation circuit in communication with each amplifier uses the amplified reference signals to provide scale factors, so as to enhance a precision of the resolver system.

Abstract: The present invention provides a circuit board having burr free castellated plated through holes. In particular, the leading edge of the plated through hole, that tends to produce burr formation during conventional profiling, is removed or pre-profiled to off-set the leading edge of the plated through hole from a surface of the circuit board.

Abstract: The present invention provides a method of creating a circuit board having burr free castellated plated through holes. In particular, the leading edge of the plated through hole, that tends to produce burr formation using conventional profiling methods, is removed or pre-profiled. The pre-profiled plated through hole is then profiled at a distance slightly off-set from the pre-profiled edge to further prevent burr formation.

Abstract: A method and apparatus for determining the angle of a shaft (16) of an electromagnetic resolver which has resolver windings (10, 12) is disclosed. The sine and cosine resolver winding signals (30, 32) are sampled at a frequency significantly greater than the resolver drive signal. A fast fourier transform (38, 40) is then applied to the winding signals. The polarity of the drive signal (42) is applied to the FFT output (44, 46) and the results are divided one into the other (52) to obtain the arctangent of the shaft angle (56). Using a multiplexer (22) the apparatus can be coupled to a large number of different electromagnetic resolvers.