Patents by Inventor Jeffrey L. Libbert

Jeffrey L. Libbert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200035544
    Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.
    Type: Application
    Filed: October 7, 2019
    Publication date: January 30, 2020
    Inventors: Henry Frank Erk, Sasha Kweskin, Jeffrey L. Libbert, Mayank Bulsara
  • Patent number: 10546771
    Abstract: A multilayer semiconductor on insulator structure is provided in which the handle substrate and an epitaxial layer in interfacial contact with the handle substrate comprise electrically active dopants of opposite type. The epitaxial layer is depleted by the handle substrate free carriers, thereby resulting in a high apparent resistivity, which improves the function of the structure in RF devices.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: January 28, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gang Wang, Jeffrey L. Libbert, Shawn George Thomas, Qingmin Liu
  • Publication number: 20200020571
    Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.
    Type: Application
    Filed: July 11, 2019
    Publication date: January 16, 2020
    Inventors: Michael R. Seacrist, Robert W. Standley, Jeffrey L. Libbert, Hariprasad Sreedharamurthy, Leif Jensen
  • Publication number: 20200020766
    Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.
    Type: Application
    Filed: June 26, 2019
    Publication date: January 16, 2020
    Inventors: Michael R. Seacrist, Robert W. Standley, Jeffrey L. Libbert, Hariprasad Sreedharamurthy, Leif Jensen
  • Patent number: 10490464
    Abstract: Methods for assessing the quality of a semiconductor structure having a charge trapping layer to, for example, determine if the structure is suitable for use as a radiofrequency device are disclosed. Embodiments of the assessing method may involve measuring an electrostatic parameter at an initial state and at an excited state in which charge carriers are generated.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: November 26, 2019
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Igor Rapoport, Srikanth Kommu, Igor Peidous, Gang Wang, Jeffrey L. Libbert
  • Patent number: 10483152
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: November 19, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Lu Fei, Jeffrey L. Libbert, Andrew M. Jones, Alex Usenko, Gang Wang, Shawn George Thomas, Srikanth Kommu
  • Patent number: 10475696
    Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: November 12, 2019
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Henry Frank Erk, Sasha Kweskin, Jeffrey L. Libbert, Mayank Bulsara
  • Patent number: 10475695
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: November 12, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Jeffrey L. Libbert
  • Patent number: 10468294
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: November 5, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Andrew M. Jones, Srikanth Kommu, Gang Wang, Jeffrey L. Libbert
  • Patent number: 10381261
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: August 13, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Jeffrey L. Libbert, Srikanth Kommu, Andrew Marquis Jones, Samuel Christopher Pratt, Horacio Josue Mendez, Leslie George Stanton, Michelle Rene Dickinson
  • Patent number: 10381260
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: August 13, 2019
    Assignee: GlobalWafers Co., Inc.
    Inventors: Igor Peidous, Jeffrey L. Libbert, Srikanth Kommu, Andrew M. Jones, Samuel Christopher Pratt, Horacio Josue Mendez, Leslie George Stanton, Michelle Rene Dickinson
  • Publication number: 20190214294
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.
    Type: Application
    Filed: March 13, 2019
    Publication date: July 11, 2019
    Inventors: Igor Peidous, Jeffrey L. Libbert
  • Publication number: 20190139818
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Inventors: Igor Peidous, Lu Fei, Jeffrey L. Libbert, Andrew M. Jones, Alex Usenko, Gang Wang, Shawn George Thomas, Srikanth Kommu
  • Patent number: 10283402
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 7, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gang Wang, Jeffrey L. Libbert, Shawn George Thomas, Igor Peidous
  • Patent number: 10269617
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: April 23, 2019
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Igor Peidous, Jeffrey L. Libbert
  • Publication number: 20190096745
    Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.
    Type: Application
    Filed: November 12, 2018
    Publication date: March 28, 2019
    Inventors: Gang Wang, Jeffrey L. Libbert, Shawn George Thomas, Igor Peidous
  • Publication number: 20190027397
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.
    Type: Application
    Filed: January 31, 2017
    Publication date: January 24, 2019
    Inventors: Igor Peidous, Andrew M. Jones, Srikanth Kommu, Gang Wang, Jeffrey L. Libbert
  • Publication number: 20190019721
    Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.
    Type: Application
    Filed: June 6, 2018
    Publication date: January 17, 2019
    Inventors: Henry Frank Erk, Sasha Kweskin, Jeffrey L. Libbert, Mayank Bulsara
  • Publication number: 20180277421
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.
    Type: Application
    Filed: May 21, 2018
    Publication date: September 27, 2018
    Inventors: Igor Peidous, Jeffrey L. Libbert, Srikanth Kommu, Andrew Marquis Jones, Samuel Christopher Pratt, Horacio Josue Mendez, Leslie George Stanton, Michelle Rene Dickinson
  • Publication number: 20180233420
    Abstract: Methods for assessing the quality of a semiconductor structure having a charge trapping layer to, for example, determine if the structure is suitable for use as a radiofrequency device are disclosed. Embodiments of the assessing method may involve measuring an electrostatic parameter at an initial state and at an excited state in which charge carriers are generated.
    Type: Application
    Filed: February 9, 2018
    Publication date: August 16, 2018
    Inventors: Igor Rapoport, Srikanth Kommu, Igor Peidous, Gang Wang, Jeffrey L. Libbert