Patents by Inventor Jeffrey L. Miller

Jeffrey L. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5931107
    Abstract: A stitching head for a computer numerically controlled stitching machine includes a thread tensioning mechanism for automatically adjusting thread tension according to the thickness of the material being stitched. The stitching head also includes a mechanism for automatically adjusting thread path geometry according to the thickness of the material being stitched.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: August 3, 1999
    Assignee: McDonnell Douglas Corporation
    Inventors: Patrick J. Thrash, Jeffrey L. Miller, Richard Codos
  • Patent number: 5915317
    Abstract: A stitching system includes a gantry that is movable along a material support table. Mounted to the gantry are a plurality of stitching heads and bobbins. The stitching heads are individually controllable in a z-direction, and the bobbins are individually controllable in the z-direction. Each stitching head is paired with a bobbin. Each pair of stitching heads and the bobbins is controlled synchronously in the z-direction. The stitching system is well-suited for stitching preforms of aircraft wing covers and other preforms having variable thickness and compound, contoured three-dimensional surfaces.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: June 29, 1999
    Inventors: Patrick J. Thrash, Jeffrey L. Miller, Kenneth G. Pallas, Robert C. Trank, Rhoda Fox, Mike Korte, Richard Codos, Aleksandr Korolev, William Collan
  • Patent number: 5627991
    Abstract: A CPU is coupled to the cache memory over a system bus having a width of 64 data bits. The cache memory is organized into a left array and a right array, with data bits stored as lines of data wherein each line is comprised of 256 data bits defined into four data "chunks" of 64 bits each. Each memory read access by the CPU to the cache results in a complete line of data to be read in the cache. The chunks comprising the line of data are coupled over an internal cache bus to a "chunk" multiplexor. The chunk multiplexor stages the data chunks in an order defined by the CPU, and sequentially send the data chunks over the system bus to the CPU. The chunks are organized as high and low order chunks. The multiplexor includes a first multiplexor for receiving the high order chunks and a second multiplexor for receiving the low order chunks.
    Type: Grant
    Filed: February 12, 1996
    Date of Patent: May 6, 1997
    Assignee: Intel Corporation
    Inventors: R. Kenneth Hose, Jr., Jeffrey L. Miller, David P. DiMarco
  • Patent number: 5473556
    Abstract: A digit reversing system is disclosed for handling mixed radix FFT operations with arbitrary arrangements of radices. In a first step, all bits in an integer field of size log.sub.2 N are position reversed. In a second step, subfields of the output produced in the first step are individually unreversed at the local level to produce unreversed digits. The output is used for appropriately arranging input terms applied to a mixed-radix multi-stage Fast Fourier Transform (FFT) process.
    Type: Grant
    Filed: September 8, 1993
    Date of Patent: December 5, 1995
    Assignees: Sharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
    Inventors: Raul A. Aguilar, Jeffrey L. Miller
  • Patent number: 4908884
    Abstract: A flexible filter drain is disclosed. The drain has a flexible body, a sealing washer, and a rigid brass drain stem with a sealing lip contacting the upper end of the body. The drain stem is held in sealing engagement with the flexible body by means of the cooperative action of an internal stem rib in the body and a rib member on the stem interlocking with the stem rib biased by the upper sealing lip on the stem cooperating with the upper surface of the body. A drain groove in the body provides fluid and contaminant flow through the drain when the lower party of the body and stem are displaced from axial alignment.
    Type: Grant
    Filed: September 19, 1988
    Date of Patent: March 20, 1990
    Assignee: The Aro Corporation
    Inventors: Scott E. John, Jeffrey L. Miller
  • Patent number: 4875196
    Abstract: An improved First-In, First-Out data buffer and method of operation incorporates a plurality of arrays of random-access memory cells in column and row orientation per array in which all the cells in a row of one array are precharged simultaneously as memory cells are accessed for read or write operations in another array. Also, all the cells in a row of the other array may be precharged as the memory cells in the one array are accessed independently for read or write operations. Accesses to memory cells in addressed rows alternate from one array to another so that the signal conditioning of the memory cells in one array can take place before access in needed and while memory cells are being accessed in another array. Improved status logic unambigously designates the conditions of empty, half full and full, independent of the sequence of data read and write operations.
    Type: Grant
    Filed: September 8, 1987
    Date of Patent: October 17, 1989
    Assignee: Sharp Microelectronic Technology, Inc.
    Inventors: Dieter W. Spaderna, Jeffrey L. Miller