Abstract: A graphics computer system including a host computer and a graphics processor. The host computer has a host data bus and a host address bus. A first video memory stores color codes corresponding to a display. The first video memory is connected to the host computer permitting it to specify the color codes. A first palette connected to the first video memory has a first look-up table memory for recalling color data words corresponding to color codes received from the first video memory. The first palette is connected to the host computer permitting it to specify the color data words stored in the first look-up table memory. The graphics processor has a local data bus and a local address bus. A second video memory stores color codes corresponding to a display, the graphics processor specifying the color codes stored in the second video memory. A second palette connected to the second video memory has a second look-up table memory.

Abstract: A multifunction access circuit for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer.

Abstract: A data memory management unit for providing cache access in a signal processing system. A programmable translation unit and an address processor are used to alter the manner in which addresses are translated and the cache is filled, respectively. The translation unit and address processor operate in accordance with a selected cache replacement mechanism, which is selected so that the cache is filled in a manner most likely to have a high hit rate for the processing algorithm currently in operation.

Abstract: A computer graphics system. The system includes a video memory having a shift register adapted for split shift register transfers, and digital computer for controlling the video memory and having a tap point counter clocked by a shift clock signal and also having a blanking circuit with a blanking output. Further, logic circuitry enabled by the blanking output is connected to initiate an extra shift clock pulse for the tap point counter during a blanking interval. Other systems, palette devices, and methods are also disclosed.

Abstract: A palette device controllable by a digital computer with a video memory having a bus for supplying multiple color codes for the palette device in each bus cycle. The palette device includes a multiple-bit input for entry of the color codes from the bus, and a look-up table memory for supplying color data words in response to the color codes from the input. Color code transfer circuitry is connected between the input and the look-up table memory to supply the look-up table memory from the input sequentially with color codes of selectable width packing the entire width of the bus. Improved palette devices, graphics computer systems, facsimile systems, printer systems and other systems and methods are also disclosed.

Abstract: A palette device for use with a digital computer that produces a video control signal and color code signals for a first bus and where the digital computer has a graphics coprocessor that produces a video control signal and color code signals for a second bus. The palette device includes an input register for holding respective bits from separate sets of input lines including a first set of input lines for signals representing color codes on the first bus and a second set of input lines for signals representing color codes on the second bus. The palette device further has a look-up table memory for supplying color data words in response to color codes from the input register, and a selector circuit connected between the input register and the look-up table memory. The selector circuit is externally controllable to transfer selected color codes from the selected first or second bus to said look-up table memory and to select a video control signal for output depending on the selected bus.

Abstract: A palette device for use with circuitry that produces color codes and a video control signal. The palette device includes a mode circuit establishing one of a plurality of different operating modes, and color code processing circuitry operable according to a mode established by the mode circuit and responsive to the color codes to supply color data words that are convertible to analog form. Depending on the different modes, the color code processing circuitry establishes different time intervals between input of the color codes to the color code processing circuitry and supplying of color data words. A digital to analog converter connected to said color code processing circuitry receives the color data words and converts them to an analog video signal.

Abstract: An integrated circuit for use with a plurality of clock oscillators. The integrated circuit has a semiconductor chip, function performing circuitry fabricated on the semiconductor chip and responsive to clock pulses provided thereto, and a semiconductor chip package having pins connected to the function performing circuitry. The integrated circuit further has a register accessible via the pins for external entry of clock control information. A clock control circuit responsive to the clock control information entered in said register has inputs connected to pins for the clock oscillators. The function performing circuitry is connected to the clock control circuit so that clock pulses are provided to the function performing circuitry by the clock control circuit in accordance with the clock control information entered in the register. Other integrated circuits, palette devices, computer graphics systems, printer systems and methods are also disclosed.

Abstract: An apparatus for graphics software development for execution in a graphics processor. The graphics processor resides in a host computer, which has a system bus and a video graphics array (VGA) for video enhanced display. The apparatus comprises a memory mapper coupled to the system bus for providing interface between the host computer and the apparatus, and a memory storage circuit coupled to the graphics processor for providing local memory space for storing data and access of the stored data. A video pass through multiplexer allows either the output of the memory storage circuit or the output of the VGA to be viewed on one monitor.