Abstract: Electronic devices and methods for fabricating electronic devices are provided. In one example, an electronic device includes an electronic device body structure having a substantially hermetically sealed cavity formed therein. A getter film is in fluid communication with the substantially hermetically sealed cavity. Conductive features are accessible from outside the substantially hermetically sealed cavity and are operatively coupled to the getter film for electrical communication with the getter film.

Abstract: Electronic devices and methods for fabricating electronic devices are provided. In one example, an electronic device includes an electronic device body structure having a substantially hermetically sealed cavity formed therein. A getter film is in fluid communication with the substantially hermetically sealed cavity. Conductive features are accessible from outside the substantially hermetically sealed cavity and are operatively coupled to the getter film for electrical communication with the getter film.

Abstract: Electronic devices and methods for fabricating electronic devices are provided. In one example, an electronic device includes an electronic device body structure having a substantially hermetically sealed cavity formed therein. A getter film is in fluid communication with the substantially hermetically sealed cavity. Conductive features are accessible from outside the substantially hermetically sealed cavity and are operatively coupled to the getter film for electrical communication with the getter film.

Abstract: Methods for evaluating semiconductor device structures are provided. In one example, a method includes forming a support layer on a first side of a lamellar sample portion of the semiconductor device structure. The lamellar sample portion has a second side opposite the first side, a target analysis area on or proximate the first side, and a first thickness defined from the first side to the second side. The second side is milled to form a reduced thickness lamellar-supported sample portion that has a milled second side opposite the first side. The support layer is removed from the reduced thickness lamellar-supported sample portion to form a reduced thickness lamellar sample portion having a second thickness that is defined from the first side to the milled second side and that is less than the first thickness. The target analysis area of the reduced thickness lamellar sample portion is evaluated.

Abstract: A method of forming and testing an interposer includes forming vias in a semiconductor material of a wafer having a front side and a back side. The method further includes disposing an electrically conductive layer on the front side of the wafer such that the layer is electrically connected to the vias. The method also includes forming electrically conductive pads on the front side of the wafer, wherein each electrically conductive pad is electrically connected to the electrically conductive layer. The method further includes forming electrically conductive bumps on the back side of the wafer, wherein each electrically conductive bump is electrically connected to at least one via. The method also includes testing electrical connectivity from a first bump to a second bump of the electrically conductive bumps.

Abstract: Methods for evaluating strain of crystalline structure are provided herein. In accordance with an exemplary embodiment, a method for evaluating strain of a crystalline structure includes directing an electron beam at the crystalline structure to produce an electron diffraction pattern including a reflection point area. The electron diffraction pattern is detected with a detector that includes a plurality of pixels to produce a raw data set. The raw data set is filtered by applying a mathematical median filter to produce a filtered data set, and a contrast of the filtered data set is enhanced to produce an enhanced data set. A center point of the reflection point area is determined with the enhanced data set, and the strain of the crystalline structure is determined based on analysis of the center point.

Abstract: Electronic devices and methods for fabricating electronic devices are provided. In one example, an electronic device includes an electronic device body structure having a substantially hermetically sealed cavity formed therein. A getter film is in fluid communication with the substantially hermetically sealed cavity. Conductive features are accessible from outside the substantially hermetically sealed cavity and are operatively coupled to the getter film for electrical communication with the getter film.

Abstract: A method of forming and testing an interposer includes forming vias in a semiconductor material of a wafer having a front side and a back side. The method further includes disposing an electrically conductive layer on the front side of the wafer such that the layer is electrically connected to the vias. The method also includes forming electrically conductive pads on the front side of the wafer, wherein each electrically conductive pad is electrically connected to the electrically conductive layer. The method further includes forming electrically conductive bumps on the back side of the wafer, wherein each electrically conductive bump is electrically connected to at least one via. The method also includes testing electrical connectivity from a first bump to a second bump of the electrically conductive bumps.

Abstract: According to an embodiment of the disclosure, a method verifies bitmap information or test data information for a semiconductor device. The method places a defect on a semiconductor device at an actual defect location using a laser to physically damage the semiconductor device. A logical address associated with the defect is detected and bitmap information or test data information is reviewed to determine an expected location corresponding to the logical address. Then, the accuracy of the bitmap information or the test data information is determined by comparing the actual defect location with the expected location. A deviation between the two indicates an inaccuracy.

Abstract: According to an embodiment of the disclosure, a method verifies bitmap information or test data information for a semiconductor device. The method places a defect on a semiconductor device at an actual defect location using a laser to physically damage the semiconductor device. A logical address associated with the defect is detected and bitmap information or test data information is reviewed to determine an expected location corresponding to the logical address. Then, the accuracy of the bitmap information or the test data information is determined by comparing the actual defect location with the expected location. A deviation between the two indicates an inaccuracy.

Abstract: A testing structure, and method of using the testing structure, where the testing structure comprised of at least one of eight test structures that exhibits a discernable defect characteristic upon voltage contrast scanning when it has at least one predetermined structural defect. The eight test structures being: 1) having an Active Area (AA)/P-N junction leakage; 2) having an isolation region to ground; 3) having an AA/P-N junction and isolation region; 4) having a gate dielectric leakage and gate to isolation region to ground; 5) having a gate dielectric leakage through AA/P-N junction to ground leakage; 6) having a gate dielectric to ground and gate/one side isolation region leakage to ground; 7) having an oversized gate dielectric through AA/P-N junction to ground leakage; and 8) having an AA/P-N junction leakage gate dielectric leakage.

Abstract: A testing structure, and method of using the testing structure, where the testing structure comprised of at least one of eight test structures that exhibits a discernable defect characteristic upon voltage contrast scanning when it has at least one predetermined structural defect. The eight test structures being: 1) having an Active Area (AA)/P-N junction leakage; 2) having an isolation region to ground; 3) having an AA/P-N junction and isolation region; 4) having a gate dielectric leakage and gate to isolation region to ground; 5) having a gate dielectric leakage through AA/P-N junction to ground leakage; 6) having a gate dielectric to ground and gate/ one side isolation region leakage to ground; 7) having an oversized gate dielectric through AA/P-N junction to ground leakage; and 8) having an AA/P-N junction leakage gate dielectric leakage.

Abstract: A method for making novel elevated bond-pad structures with sidewall spacers is achieved. The elevated bond-pad structures increase the space between the chip and a substrate during flip-chip bonding. The increased spacing results in better under-filling and reduces alpha particle soft errors in the chip. The sidewall spacers restrict the wetting surface for the PbSn solder bumps to the top surface of the bond pads. This results in smaller solder bumps and allows for closer spacings of the array of bonding pads for higher density integrated circuits.

Abstract: A method for making novel elevated bond-pad structures with sidewall spacers is achieved. The elevated bond-pad structures increase the space between the chip and a substrate during flip-chip bonding. The increased spacing results in better under-filling and reduces alpha particle soft errors in the chip. The sidewall spacers restrict the wetting surface for the PbSn solder bumps to the top surface of the bond pads. This results in smaller solder bumps and allows for closer spacings of the array of bonding pads for higher density integrated circuits.