Abstract: An integrated circuit comprising interconnects located in a layer on a semiconductor substrate. The circuit also comprises dummy-fill-structures located between the interconnects in the layer. The dummy-fill-structures form a plurality of fiducials, each of the fiducials being located in a different region of the layer. Each fiducial comprises a pre-defined recognition pattern that is different from every other fiducial in adjacent regions of the layer.

Abstract: An embodiment of the invention is a method of integrated circuit repair that includes removing the top dielectric layer 160 in at least one location using a FIB and etching exposed areas of a top metal layer 171 using a wet chemistry process. This method also includes etching selected portions of one or more dielectric interconnect layers 140, 141 using a FIB, and then using a FIB to either cut a selected portion of a metal interconnect layer 130, 131 or connect a selected portion of a metal interconnect layer 130, 131. Another embodiment of the invention is a method of integrated circuit repair that forms a top dielectric layer 80 over the circuit 10 and then removes the top dielectric layer 80 in at least one location using a FIB. The exposed areas of a top metal layer 70 are etched using a wet chemistry process.