Patents by Inventor Jeffrey Lee Large

Jeffrey Lee Large has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967569
    Abstract: A method includes attaching a first portion of a preformed metal micro-wire to a multilayer structure. The preformed metal micro-wire has a diameter of 10 microns or less. The method also includes attaching a second portion of the preformed metal micro-wire to the multilayer structure.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: April 23, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Michael Lee Dawson, Edward J. Pryor, III, Jeffrey L. Large, Mary Coles
  • Patent number: 8330159
    Abstract: An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: December 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey Lee Large, Henry Litzmann Edwards, Ayman A. Fayed, Patrick Cruise, Kah Mun Low, Neeraj Nayak, Oguz Altun, Chris Barr
  • Publication number: 20090114912
    Abstract: An integrated circuit (IC) includes a substrate having a device layer and a plurality of metal layers formed thereon. The plurality of metal layers include patterned upper metal layers and lower metal layers, a multi-level metal interconnect structure formed using the plurality of metal layers, where the interconnect structure is in electrical contact with a first portion and second portion of the device layer. At least one circuit editing structure including a first and second columns are formed using at least a portion of the plurality of metal layers, the first column being in electrical contact with the first portion of the device layer and the second column being in electrical contact with second portion of the device layer, where a portion of the first and second columns define a circuit editing feature operable to electrically couple or decouple the columns using focused ion beam (FIB) processing.
    Type: Application
    Filed: November 1, 2007
    Publication date: May 7, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Jeffrey Lee Large, Henry Litzmann Edwards, Ayman A. Fayed, Patrick Cruise, Kah Mun Low, Neeraj Nayak, Oguz Altun, Chris Barr