Abstract: This invention relates to a chip package structure comprising of a chip, multiple leads with inner and outer ends, an exposed chip upper surface, an encapsulated body encloses the peripherals of the chip, and multiple conducting wires used to connect electrically the chip and leads, wherein said leads extends internally to the surfaces on the two sides of the chip, in the mean time, pasting method is used to connect the two side surfaces of the chip to the leads in order to carry the chip, therefore, traditional die pad is replaced, furthermore, the outer ends or lower surfaces of the leads are exposed out of encapsulated body, this is to prevent solder overflow and enhance solder aggregation effect, in the mean time, packaging cost can be saved and easier visual positioning and rework can be obtained from this package structure, leads are used as terminals to be electrically connected to the external; therefore, through the internally extended leads structure, die pad is replaced, and the effects of package

Abstract: The present invention provides a chip assembly structure with a cover, comprising: a socket having four sidewalls to form a room for placing a chip and comprising a plurality of contact ends corresponding to the contacts of the chip to be placed, wherein each contact ends penetrates said socket to form an exposing solder terminal; and a cover having at least a flexible part against on the chip when the chip is positioned in the room.

Abstract: A fine-sized chip package structure is disclosed to include a memory chip, a leadframe having a plurality of leads bilaterally arranged on the bottom surface of the memory chip, gold wires connected between respective bonding pads at the middle part of the bottom surface of the memory chip and respective stitches at the bottom surface of each rectangular block-like lead of the leadframe, and a molding compound locally molded on a part of the memory chip and a part of each leadframe with a difference of elevation between the bottom surface of the molding compound and the bottom surfaces of the leads of the leadframe for receiving a solder material used to bond the memory chip and the leadframe to a circuit board, preventing overflow of the solder material during bonding of the memory chip and the leadframe to the circuit board.

Abstract: A manufacturing method of a modularized leadframe, using a first mold set to contact and hold the upper surface of rows of multiple block leads, using a second mold set to contact and hold at least one selected surface of the lower surface of leads, the second mold set has a protruding part between each row of leads so that the upper surface of the protruding part be in close contact with the inner surface of the first mold set. The hollow space between the mold sets is then injected with packaging materials such that a leadframe structure having packaged and fixed leads therein and surfaces for wire-bonding and soldering is obtained. A packaging material filling space is formed in the leadframe after removing the first and the second mold sets.

Abstract: A method of fabricating a high-density lead arrangement package structure is disclosed. The first process of the packaging structure is packaging a chip, a plurality of leads and a plurality of metallic bonding wires by encapsulant such that conducting surfaces are formed at lower surfaces of the leads. The second process of the packaging structure is selectively forming insulation portions on the conducting surfaces of the leads according to the position of contact points on a circuit board. Thus, the overall fabrication cost of the chip package may be effectively reduced. Furthermore, the process of the packaging structure of the present invention is simple and is capable of increasing both the production yield and the reliability of the chip package device.

Abstract: A concealable chip leadframe unit structure is disclosed which is made up of multiple lead units arranged in order, each lead in the lead unit is formed by pressing and comprising of a piece body with upper placement plane, the lower surface of the piece body is pressed to form at least an inner conducting plane which can be connected to the chip, and at least one protruding bump is formed adjacent to the inner conducting plane, the end surface of the protruding bump is used as an out-conducting plane to be connected to outside; in this structure, chip can be attached to the upper placement plane of the lead structure, and the inner conducting plane can be connected to the chip through metallic wire.

Abstract: A packaging method for integrated circuits comprising processes such as wafer grinding, wafer mount, wafer saw, die attach, etc., multiple singulated chips are each attached and assembled to leadframe unit, the leadframe unit is used as electrical out-connecting component for each chip, and the wire-bonding part of the chip is dispensed continuously with encapsulant material to seal, curing method is further applied to solidify the encapsulant, then saw or punching method is used to dice apart each chip accompanied with leadframe unit (singulation process), a ready-to-use integrated circuit is thus obtained, such manufacturing processes let the goals of easy-to-manufacture, fast production and lowered-production cost be easily achieved for the packaging and singulating processes.

Abstract: A method of forming precision leads on a chip-supporting leadframe includes the step of having each of the leads plated at a lower side with a metal substance to directly form one or more conducting sections and outer conducting planes, such that the non-plated area of the lower side of each lead defines an inner conducting plane for electrically conductively contacting with a chip supported on a top of the leadframe. The conducting sections and the outer conducting planes directly plated on the leads have precise and stable sizes and allow the leadframe to have a reduced volume. The metal substance for plating maybe gold, silver, copper, etc., depending on actual need, so as to increase the conductivity and reduce the resistance of the leads.

Abstract: A packaging method for integrated circuits comprising processes such as wafer grinding, wafer mount, wafer saw, die attach, etc., multiple singulated chips are each attached and assembled to leadframe unit, the leadframe unit is used as electrical out-connecting component for each chip, and the wire-bonding part of the chip is dispensed continuously with encapsulant material to seal, curing method is further applied to solidify the encapsulant, then saw or punching method is used to dice apart each chip accompanied with leadframe unit (singulation process), a ready-to-use integrated circuit is thus obtained, such manufacturing processes let the goals of easy-to-manufacture, fast production and lowered-production cost be easily achieved for the packaging and singulating processes.

Abstract: A chip fixed structure which is aiming at the better design of the adhesive body between the chip and the finger of the lead frame as well as its composite structure, which is to make said adhesive body with adhesion to form the stripe shapes with its width relatively smaller than the finger, through this to paste & settles a plurality of adhesive body on the upper lead facet of its dual-arrows or four-arrows fingers, also makes a chip pasting on the adhesive body which makes each arrow of lead frame carrying a chip and composite a fixed adhesive structure, so that it forms a structure with its width relatively smaller than the lead frame through said adhesive body as well as its composite formation, which allows the physical or chemical influences by the temperature change, thus maintaining the quality of chip as well as its usage lives.

Abstract: A high density lead arrangement package structure is disclosed, it is related an improvement on traditional leadframe staggered arranged leads, the leadframe contains multiple rows arrangement of block leads, at least one conducting surface is formed at the bottom side of leads, the conducting surface of leads is specifically selected and installed with at least one insulator, the insulator on the leads are arranged in spaced and staggered way such that the exposed conducting surface of neighboring insulators is arranged in spaced and staggered way too, leads which are arranged in high density way and easily to be manufactured are thus formed.

Abstract: A miniaturized chip scale package is provided for the improvement of conventional chip package issues such as bulky packaged volume and bad heat dissipation. This invention provides a leadframe comprising multiple block leads for semiconductor die attachment. Conducting metallic wires are used to connect all the block leads of the leadframe to the chip, then the metallic conducting wire part is specifically encapsulated with insulating material to further form a miniaturized encapsulated body. The encapsulated body fully enclose the wire bonding part and at least an out-connecting electrical conducting part is preserved on the lower part of the lead such that the final packaged volume is reduced, heat dissipation efficiency is enhanced, and the chip transfer speed to the outside is enhanced due to a reduction in the transfer distance by the rectangular block leads structure design.

Abstract: A semiconductor chip leadframe module is disclosed, it is to provide selectively installed and directly connected common electrical leads among multiple leadframe units, and to provide independent electrical leads which can be connected respectively to circuit board (such as printed circuit board), the leadframe module thus formed provide space for the assembly of multiple chips, and the common signals on the chips can be connected to common electrical leads and then transferred to the circuit board, in contrary, the independent signals are transferred by the circuit board through independent electrical leads, the circuit board used layers and the amount of circuit layouts can thus be reduced, circuit board of lighter weight and smaller form factor can thus be achieved, furthermore, the saving in the usage of the circuit board space further provides more room for the plan and implementation of other functional structures or devices, etc.

Abstract: A concealable chip leadframe unit structure is disclosed which is made up of multiple lead units arranged in order, each lead in the lead unit is formed by pressing and comprising of a piece body with upper placement plane, the lower surface of the piece body is pressed to form at least an inner conducting plane which can be connected to the chip, and at least one protruding bump is formed adjacent to the inner conducting plane, the end surface of the protruding bump is used as an out-conducting plane to be connected to outside; in this structure, chip can be attached to the upper placement plane of the lead structure, and the inner conducting plane can be connected to the chip through metallic wire.

Abstract: A manufacturing method of a modularized leadframe, using a first mold set to paste and hold the upper surface of rows of multiple block leads, using a second mold set to paste and hold at least one selected surface of the lower surface of leads, let second mold set form a protruding part among each row of leads, let the surface of the protruding part be in close contact with the inner surface of the first mold set, then the hollow space between mold sets is injected with packaging materials such that a leadframe structure is formed with leads fixed and wire-bonding surface and soldering surface exposed ,a hollow space is formed in the leadframe for later wire-bonding operation after chip is attached in the space.

Abstract: The present invention relates to the structural design of a circuit board having deposit holes. The design is to allocate one or more deposit holes that are either caved in or penetrate through the board at locations specified by the spatial layout, as well as to set step-like holes on a multilayer circuit board. On the panel surrounding the edge of the deposit holes, circuit contacts are provided for connecting electronic components (for example IC transistors, connectors, resistors, capacitors, or other circuit boards), such that when placed in deposit holes, they can be welded or fixed via the circuit contacts.

Abstract: The present invention is related to an assembly structure for hiding electronic components, that is, at least one containing hole penetrating through a PCB being set on a predetermined location of the PCB, circuits being arranged on at least one surface of a predetermined side edge of the containing hole, the containing hole being capable of reserving at least one electronic component (IC chip, resistance, capacitance or LED, etc.) so as to that at least one leg of the electronic component extending and connecting to the circuits of the surface for welding, the assembly structure for hiding electronic components is therefore formed.

Abstract: The present invention is related to a switching media for chip carrier device, the switching media has a flexible board, the flexible board has circuits and a plurality of connecting points by way of etching thereon, the connecting points are able to connect to any type of chip of integrated circuit electrically, another plurality of etched connecting points on a lower surface of the flexible board are capable of connecting to the chip carrier device electrically, the circuits thereon individually connect to the connecting points on an upper surface of the flexible board and the connecting points on the lower surface. It is convenient for that the flexible board can electrically connect to the chip carrier device while the flexible board is installed on the chip carrier device. Hence, the upper surface is able to be mounted by any type of integrated circuit chip to reach the purposes of any chip connecting to the chip carrier device by means of the flexible board and any chip being changeable anytime.

Abstract: This invention relates to a chip package structure comprising of a chip, multiple leads with inner and outer ends, an exposed chip upper surface, an encapsulated body encloses the peripherals of the chip, and multiple conducting wires used to connect electrically the chip and leads, wherein said leads extends inward to the surfaces on the two sides of the chip, in the mean time, pasting method is used to connect the two side surfaces of the chip to the leads in order to carry the chip, therefore, traditional die pad is replaced, furthermore, the outer ends or surfaces of the leads are exposed out of encapsulated body, this is to prevent solder overflow and enhance solder aggregation effect, in the mean time, packaging cost can be saved and easier visual positioning and rework can be obtained from this package structure, leads are used as terminals to be electrically connected to the external; therefore, through the inward extended leads structure, die pad is replaced, and the effects of package volume reducti