Abstract: A method of forming a magnetoresistive random access memory (MRAM) device includes providing a first die containing a selector material layer located over a first substrate, providing a second die containing a MRAM layer stack located over a second substrate, and bonding the first die to the second die.

Abstract: A refractory metal-containing etch stop layer, a ruthenium etch stop layer, and a conductive material layer can be sequentially formed over an electrode layer and a selector material layer. A sequence of anisotropic etch processes can be employed to etch the conductive material layer selective to the ruthenium etch stop layer, to etch the ruthenium etch stop layer selective to the refractory metal-containing etch stop layer, and to etch the refractory metal-containing etch stop layer within minimal overetch into the electrode layer. The selector material layer can be subsequently anisotropically etched without exposure to the plasma of etchant gases for etching the refractory metal-containing etch stop layer and the conductive material layer, which may include a fluorine-containing plasma that can damage the selector material.

Abstract: A refractory metal-containing etch stop layer, a ruthenium etch stop layer, and a conductive material layer can be sequentially formed over an electrode layer and a selector material layer. A sequence of anisotropic etch processes can be employed to etch the conductive material layer selective to the ruthenium etch stop layer, to etch the ruthenium etch stop layer selective to the refractory metal-containing etch stop layer, and to etch the refractory metal-containing etch stop layer within minimal overreach into the electrode layer. The selector material layer can be subsequently anisotropically etched without exposure to the plasma of etchant gases for etching the refractory metal-containing etch stop layer and the conductive material layer, which may include a fluorine-containing plasma that can damage the selector material.

Abstract: A Magnetoresistive Random Access Memory (MRAM) assembly includes a substrate, a plurality of MRAM cells, a plurality of bit lines, each bit line magnetically coupled to one of the plurality of MRAM cells, a plurality of word lines, each word line magnetically coupled to one of the plurality of MRAM cells, a first planar ferromagnetic shielding component located vertically above the substrate such that the plurality of bit lines and the plurality of word lines are located between the first planar ferromagnetic shielding component and the substrate, and a first insulating layer located between the first ferromagnetic shielding component and one of the bit lines or word lines such that the bit lines or word lines are not electrically connected to the first ferromagnetic shielding component.

Abstract: A Magnetoresistive Random Access Memory (MRAM) assembly includes a substrate, a plurality of MRAM cells, a plurality of bit lines, each bit line magnetically coupled to one of the plurality of MRAM cells, a plurality of word lines, each word line magnetically coupled to one of the plurality of MRAM cells, a first planar ferromagnetic shielding component located vertically above the substrate such that the plurality of bit lines and the plurality of word lines are located between the first planar ferromagnetic shielding component and the substrate, and a first insulating layer located between the first ferromagnetic shielding component and one of the bit lines or word lines such that the bit lines or word lines are not electrically connected to the first ferromagnetic shielding component.

Abstract: Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.

Abstract: A Magnetoresistive Random Access Memory (MRAM) assembly includes a first ferromagnetic shielding component, a second ferromagnetic shielding component, a plurality of MRAM cells located between the first and second ferromagnetic shielding components, a plurality of bit lines located between the first and second ferromagnetic shielding components, each bit line coupled to at least one of the plurality of MRAM cells, a plurality of word lines located between the first and second ferromagnetic shielding components, each word line coupled to at least one of the plurality of MRAM cells, a ferromagnetic yoke electrically connecting the first and second ferromagnetic shielding components, and located in an area of the assembly substantially free of the MRAM cells, bit lines, and word lines, and an insulator surrounding the magnetic yoke.

Abstract: Resistive memory cells containing nanoparticles are formed between two electrodes. The nanoparticles may be embedded in a matrix or sintered together without a matrix. The memory cells may be projected memory cells or barrier modulated cells. Polymeric ligands may be used to deposit the nanoparticles over a substrate, followed by an optional removal or replacement of the polymeric ligands.

Abstract: The present disclosure generally relates to a structure, system, and method for manufacturing an electrical component for a memory device. For example, depositing alternating layers of conductive and insulator materials over an etch stop layer to create a vertical stack, etching a trench through the vertical stack to expose the etch stop layer, electroplating the conductive layers using a plating material based on a desired electrical behavior, and forming a connection between the plating materials for each of the conductive layers.

Abstract: Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.

Abstract: Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers. A plurality of vias is formed through the vertical stack from the top layer to the bottom layer. A memory layer disposed adjacent the conductive layers in the vias. A selector device disposed adjacent the memory layer wherein the selector device comprises multiple layers of dissimilar metal oxides. A lateral electrical contact to the memory layer through the conductive layer. And a top contact electrically connected to the conductive layer through a portion of the memory layer and the portion of the memory layer wherein the portion of the memory layer is configured to store data therein.

Abstract: Resistive memory cells containing nanoparticles are formed between two electrodes. The nanoparticles may be embedded in a matrix or sintered together without a matrix. The memory cells may be projected memory cells or barrier modulated cells. Polymeric ligands may be used to deposit the nanoparticles over a substrate, followed by an optional removal or replacement of the polymeric ligands.

Abstract: Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.

Abstract: Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers. A plurality of vias is formed through the vertical stack from the top layer to the bottom layer. A memory layer disposed adjacent the conductive layers in the vias. A selector device disposed adjacent the memory layer wherein the selector device comprises multiple layers of dissimilar metal oxides. A lateral electrical contact to the memory layer through the conductive layer. And a top contact electrically connected to the conductive layer through a portion of the memory layer and the portion of the memory layer wherein the portion of the memory layer is configured to store data therein.

Abstract: Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers. A plurality of vias is formed through the vertical stack from the top layer to the bottom layer. A memory layer disposed adjacent the conductive layers in the vias. A selector device disposed adjacent the memory layer wherein the selector device comprises multiple layers of dissimilar metal oxides. A lateral electrical contact to the memory layer through the conductive layer. And a top contact electrically connected to the conductive layer through a portion of the memory layer and the portion of the memory layer wherein the portion of the memory layer is configured to store data therein.

Abstract: Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.

Abstract: The present disclosure generally relates to a structure, system, and method for manufacturing an electrical component for a memory device. For example, depositing alternating layers of conductive and insulator materials over an etch stop layer to create a vertical stack, etching a trench through the vertical stack to expose the etch stop layer, electroplating the conductive layers using a plating material based on a desired electrical behavior, and forming a connection between the plating materials for each of the conductive layers.

Abstract: Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.

Abstract: The present disclosure generally relates to a structure, system, and method for manufacturing an electrical component for a memory device. For example, depositing alternating layers of conductive and insulator materials over an etch stop layer to create a vertical stack, etching a trench through the vertical stack to expose the etch stop layer, electroplating the conductive layers using a plating material based on a desired electrical behavior, and forming a connection between the plating materials for each of the conductive layers.

Abstract: The present disclosure generally relates to a structure, system, and method for manufacturing an electrical component for a memory device. For example, depositing alternating layers of conductive and insulator materials over an etch stop layer to create a vertical stack, etching a trench through the vertical stack to expose the etch stop layer, electroplating the conductive layers using a plating material based on a desired electrical behavior, and forming a connection between the plating materials for each of the conductive layers.