Patents by Inventor Jeffrey Louis Hurd

Jeffrey Louis Hurd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electroplated interconnection structures on integrated circuit chips
    Patent number: 6946716
    Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: September 20, 2005
    Assignee: International Business Machines Corporation
    Inventors: Panayotis Constantinou Andricacos, Harikilia Deligianni, John Owen Dukovic, Daniel C. Edelstein, Wilma Jean Horkans, Chao-Kun Hu, Jeffrey Louis Hurd, Kenneth P. Rodbell, Cyprian Emeka Uzoh, Kwong-Hon Wong
  • Electroplated interconnection structures on integrated circuit chips
    Publication number: 20040229456
    Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
    Type: Application
    Filed: February 9, 2004
    Publication date: November 18, 2004
    Applicant: International Business Machines
    Inventors: Panayotis Constantinou Andricacos, Hariklia Deligianni, John Owen Dukovic, Daniel Charles Edelstein, Wilma Jean Horkans, Chao-Kun Hu, Jeffrey Louis Hurd, Kenneth Parker Rodbell, Cyprian Emeka Uzoh, Kwong-Hon Wong
  • Method of making electroplated interconnection structures on integrated circuit chips
    Patent number: 6709562
    Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of Cu electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
    Type: Grant
    Filed: July 6, 1999
    Date of Patent: March 23, 2004
    Assignee: International Business Machines Corporation
    Inventors: Panayotis Constantinou Andricacos, Hariklia Deligianni, John Owen Dukovic, Daniel Charles Edelstein, Wilma Jean Horkans, Chao-Kun Hu, Jeffrey Louis Hurd, Kenneth Parker Rodbell, Cyprian Emeka Uzoh, Kwong-Hon Wong