Abstract: A central processing unit (CPU) 10 comprises an external control memory for storing microinstructions which correspond to macroinstructions read from a system memory. The microinstructions are 56 bits in length and are read in 28-bit segments. CPU 10 also comprises an internal memory management unit (MMU) 18 which comprises a plurality of address translation entry (ATE) registers four of which are permanent and sixteen of which are temporary in that the storage of a new translation entry occurs in a least recently used temporary translation entry register. CPU 10 also comprises a plurality of status register bits, some of which are settable only by predefined microinstructions. All of the status register bits are branchable. CPU 10 further comprises a condition code register the state of which may be determined by input signal pins. CPU 10 also comprises address generation logic which may generate a 24, 31 or 32 bit address upon a 32-bit address bus.

Abstract: A technique for providing electrostatic discharge (ESD) protection for an open-drain CMOS I/O buffer circuit. having an output terminal. An NMOS enhancement-mode transistor has its drain connected to the VDD power bus for the buffer circuit, its source connected to the output terminal, and its gate connected to a noise-free internal VSS power bus (VSSI). The bulk region is connected to the VSS power bus (VSSE) for the I/O buffer circuit. ESD protection is provided by a parasitic lateral npn bipolar transistor that is inherent to the NMOS transistor. The parasitic lateral npn bipolar transistor has an emitter formed from the drain-to-bulk junction of the NMOS transistor, a collector formed from the source-to-bulk junction of the NMOS transistor, and a base formed in the bulk region.

Abstract: A first-in, first out data memory minimizes fall-through delay. The FIFO memory has a plurality of cascaded register stages arranged in sections, with the input of each section selectively coupled to a bypass bus. Data is introduced on the bypass bus, and control logic writes the data into the section nearest the output which is currently not full. The individual register stages are self-clocked, so that data is then shifted toward the output through any vacant registers. In another aspect, the register stages are arranged in sections of different length, with the shortes section closest to the output and the longest section closest to the input. Decreased fall-through delay is achieved by minimizing the length of the FIFO buffer actually traversed by the data while insuring that the order of the data remains unchanged.

Abstract: An improved NMOS storage cell for use in shift registers is disclosed. Among other components, it contains a pair of inverters--one them an enabling inverter. A pre-charge transistor is placed in parallel with the first inverter to decrease the rise time associated with the transition from a logic low level output to a logic high level output. The result of adding the pre-charge transistor to the circuit is to increase the speed of operation of the storage cell, without the accompanying decrease in density with prior art methods, where the components must be enlarged. Another aspect of the present invention which further increases the density of the cell is the elimination of the complement clock line found in many prior art storage cells. The previous combination of a second inverter and a pass transistor connected to a complement clock line, is replaced by an enabling inverter connected to the clock line.

Abstract: A watch circuit arrangement for conserving battery power includes a feedback connection between the crystal oscillator of the watch circuit and the display voltage generator which is responsive to the crystal oscillator output to develop sufficient output voltage for the watch display. Specifically, the output of the display voltage generator, which may be a voltage multiplier, is sensed by a display voltage sensing circuit which controls the gain of the crystal oscillator. Initially, when battery power is applied to the watch circuit, the voltage multiplier has zero output voltage, which conditions the crystal oscillator to have a sufficiently high gain to start the oscillator. After several cycles of oscillator signal, the voltage multiplier output increases, which conditions the crystal oscillator to have a lower gain for reducing power consumption while sustaining oscillation.