Abstract: A robotic soil sampling assembly for rapidly obtaining a soil sample from each of multiple sites includes a rolling chassis, to which a sampling apparatus and a computer are attached. The sampling apparatus comprises an auger, a plurality of containers, a robotic manager, and a robotic handler. The robotic manager selectively positions a respective container in axial alignment with the auger, whereupon it is selectively gripped by the robotic handler and selectively positioned along an axis that is defined by the auger. A drill motor and a drill actuator selectively rotate and drill the auger, respectively, into ground upon which the rolling chassis is positioned. The computer is programmed to selectively actuate a pair of chassis motors to sequentially position the rolling chassis at sampling sites and to selectively actuate the sampling apparatus for obtaining a soil sample, which is deposited into an associated container.

Abstract: In one aspect, a method includes forming an electrical path between p-type mercury cadmium telluride and a metal layer. The forming of the electrical path includes depositing a layer of polycrystalline p-type silicon directly on to the p-type mercury cadmium telluride and forming the metal layer on the layer of polycrystalline p-type silicon. In another aspect, an apparatus includes an electrical path. The electrical path includes a p-type mercury cadmium telluride layer, a polycrystalline p-type silicon layer in direct contact with the p-type mercury cadmium telluride layer, a metal silicide in direct contact with the polycrystalline p-type silicon layer, and an electrically conductive metal on the metal silicide. In operation, holes, indicative of electrical current on the electrical path, flow from the p-type mercury cadmium telluride layer to the electrically conductive metal.

Abstract: In one aspect, a method includes forming an electrical path between p-type mercury cadmium telluride and a metal layer. The forming of the electrical path includes depositing a layer of polycrystalline p-type silicon directly on to the p-type mercury cadmium telluride and forming the metal layer on the layer of polycrystalline p-type silicon. In another aspect, an apparatus includes an electrical path. The electrical path includes a p-type mercury cadmium telluride layer, a polycrystalline p-type silicon layer in direct contact with the p-type mercury cadmium telluride layer, a metal silicide in direct contact with the polycrystalline p-type silicon layer, and an electrically conductive metal on the metal silicide. In operation, holes, indicative of electrical current on the electrical path, flow from the p-type mercury cadmium telluride layer to the electrically conductive metal.

Abstract: A semiconductor structure having a first semiconductor body having an upper surface with a non <211> crystallographic orientation and a second semiconductor body having a surface with a <211> crystallographic orientation, the surface of the second semiconductor body being bonded to a bottom surface of the first semiconductor body. A layer comprising CdTe is epitaxially disposed on the upper surface of the second semiconductor body. The second semiconductor body is CZ silicon, has a thickness less than 10 microns and has a diameter of at least eight inches. A getter having micro-cavities has a bottom surface formed on an upper surface of the first semiconductor body and has an upper surface bonded to a bottom surface of the second semiconductor body.

Abstract: A semiconductor structure having a first semiconductor body having an upper surface with a non <211> crystallographic orientation and a second semiconductor body having a surface with a <211> crystallographic orientation, the surface of the second semiconductor body being bonded to a bottom surface of the first semiconductor body. A layer comprising CdTe is epitaxially disposed on the upper surface of the second semiconductor body. The second semiconductor body is CZ silicon, has a thickness less than 10 microns and has a diameter of at least eight inches. A getter having micro-cavities has a bottom surface formed on an upper surface of the first semiconductor body and has an upper surface bonded to a bottom surface of the second semiconductor body.

Abstract: A semiconductor structure having a first semiconductor body having an upper surface with a non <211>crystallographic orientation and a second semiconductor body having a surface with a <211>crystallographic orientation, the surface of the second semiconductor body being bonded to a bottom surface of the first semiconductor body. A layer comprising CdTe is epitaxially disposed on the upper surface of the second semiconductor body. The second semiconductor body is CZ silicon, has a thickness less than 10 microns and has a diameter of at least eight inches. A getter having micro-cavities has a bottom surface formed on an upper surface of the first semiconductor body and has an upper surface bonded to a bottom surface of the second semiconductor body.

Abstract: In one embodiment, a method of preparing detectors for oxide bonding to an integrated chip, e.g., a readout integrated chip, includes providing a wafer having a plurality of detector elements with bumps thereon. A floating oxide layer is formed surrounding each of the bumps at a top portion thereof. An oxide-to-oxide bond is formed between the floating oxide layer and an oxide layer of the integrated chip which is provided in between corresponding bumps of the integrated chip. The oxide-to-oxide bond enables the bumps on the detector elements and the bumps on the integrated chip to be intimately contacted with each other, and removes essentially all mechanical stresses on and between the bumps. In another embodiment, a device has an interconnect interface that includes the oxide-to-oxide bond and an electrical connection between the bumps on the detector elements and the bumps on the integrated chip.

Abstract: A wafer bonded composite structure is provided for matching a coefficient of thermal expansion of a first semiconductor chip to a coefficient of thermal expansion of a second semiconductor chip in order to provide a thermally matched hybridized semiconductor chip assembly. The wafer bonded composite structure includes a first semiconductor chip having a top and a bottom surface. The first semiconductor chip has a coefficient of thermal expansion which is less than the coefficient of thermal expansion of the second semiconductor chip. Preferably, the first semiconductor chip is an readout integrated circuit (ROIC) and the second semiconductor chip is an infrared detector chip. Further, the wafer bonded composite structure also includes a substrate wafer bonded to a bottom surface of the first semiconductor chip to form the wafer bonded composite structure itself.

Abstract: In one embodiment, a method of preparing detectors for oxide bonding to an integrated chip, e.g., a readout integrated chip, includes providing a wafer having a plurality of detector elements with bumps thereon. A floating oxide layer is formed surrounding each of the bumps at a top portion thereof. An oxide-to-oxide bond is formed between the floating oxide layer and an oxide layer of the integrated chip which is provided in between corresponding bumps of the integrated chip. The oxide-to-oxide bond enables the bumps on the detector elements and the bumps on the integrated chip to be intimately contacted with each other, and removes essentially all mechanical stresses on and between the bumps. In another embodiment, a device has an interconnect interface that includes the oxide-to-oxide bond and an electrical connection between the bumps on the detector elements and the bumps on the integrated chip.

Abstract: A wafer structure is deposited on a composite substrate structure having at least two substrate layers bonded together. A first substrate layer is made of a first substrate material having a first-substrate-layer material transverse coefficient of thermal expansion, greater than the wafer transverse coefficient of thermal expansion, and a second substrate layer is made of a second substrate material having a second-substrate-layer material transverse coefficient of thermal expansion, measured parallel to the transverse direction, less than the wafer transverse coefficient of thermal expansion. The substrate layers are present in relative proportions such that the substrate transverse coefficient of thermal expansion differs from the wafer transverse coefficient of thermal expansion by not more than about 2×10?6/° F.

Abstract: A wafer structure is deposited on a composite substrate structure having at least two substrate layers bonded together. A first substrate layer is made of a first substrate material having a first-substrate-layer material transverse coefficient of thermal expansion, greater than the wafer transverse coefficient of thermal expansion, and a second substrate layer is made of a second substrate material having a second-substrate-layer material transverse coefficient of thermal expansion, measured parallel to the transverse direction, less than the wafer transverse coefficient of thermal expansion. The substrate layers are present in relative proportions such that the substrate transverse coefficient of thermal expansion differs from the wafer transverse coefficient of thermal expansion by not more than about 2×10−6/° F.

Abstract: A towing system for a vehicle particularly suited for a vehicle having an energy absorbing feature. The towing system has a frame bracket mounted to a frame member and bumper bracket, e.g., mounted to a bumper or bumper strut. The frame bracket and bumper brackets are mounted strategic one to the other and in a paired relation. The brackets are mounted at determined positions so that the energy absorbing feature of the vehicle is not compromised. A draw tube is removably mountable in each bracket pair. The draw tube is installed for the mounting of a tow bar and is removed to restore the energy absorbing feature of the vehicle.

Abstract: A method and apparatus for projecting multiple patches of full spectrum, rainbow colors to multiple, widely distributed locations is provided. The invention enables the display of such patches on a surface area toward which a source of light is directed, for example the walls and ceiling of a room from sunlight entering the room through a window in the room. The method and apparatus provide first for the refraction of the light from the source of light, and secondly for both the refraction and the reflection of the initially refracted light. The initially refracted light is projected onto a surface of the room as main multiple spectral patches; and the refracted-refracted light, and the reflected-refracted light are projected onto other surfaces of the room laterally of the main patches as additional spectral patches, creating in all, multiple spectral displays of full spectrum, rainbow colors nearly surrounding a viewer and changing in position and shapes with the movement of the sun or other light source.

Abstract: A clamp arm for attachment to the plunger of a clamping cylinder has a body with a central opening for receiving the plunger and a working arm portion extending outwardly from the opening. The body has a radial slot extending from the central opening and a bore in the body that extends transversely through the slot. One portion of the bore is threaded to receive a headed bolt to draw the sides of the slot together to lock the body on the plunger. The body is axially restrained on the plunger by means of a ring received in a counter bore above the transverse bore for the headed bolt. The ring is received in a circumferential groove in the plunger. Alternatively, the headed bolt that is used to draw the sides of the slot together engages a circumferential groove in the plunger.