Patents by Inventor Jeffrey M. Thomas

Jeffrey M. Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130223041
    Abstract: A low profile, space efficient circuit shield is disclosed. The shield includes top and bottom metal layers disposed on the top of and below an integrated circuit. In one embodiment the shield can include edge plating arranged to encircle the edges of the integrated circuit and couple the top and bottom metal layers together. In another embodiment, the shield can include through vias arranged to encircle the edges of the integrated circuit and couple the top and bottom metal layers together. In yet another embodiment, passive components can be disposed adjacent to the integrated circuit within the shield.
    Type: Application
    Filed: August 23, 2012
    Publication date: August 29, 2013
    Applicant: Apple Inc.
    Inventors: Shawn X. Arnold, Scott P. Mullins, Jeffrey M. Thoma, Ram Chandhrasekhar
  • Publication number: 20130201615
    Abstract: Stacked arrays of components are disclosed. In one embodiment, a first and a second layer of components are electrically and mechanically coupled to an interposer with an encapsulated third layer of components disposed between the first and second layers. The first layer can be configured to attach the stacked array to a host printed circuit board. The interposer can couple signals between the components on the first and second layers.
    Type: Application
    Filed: August 22, 2012
    Publication date: August 8, 2013
    Applicant: APPLE INC.
    Inventors: Shawn X. ARNOLD, Douglas P. KIDD, Sean A. MAYO, Scott P. MULLINS, Dennis R. PYPER, Jeffrey M. THOMA, Kenyu TOJIMA
  • Publication number: 20130201616
    Abstract: Stacked arrays of components are disclosed. In one embodiment, a first and a second layer of components are electrically and mechanically coupled to a thin interposer disposed between the first and second layers. The first layer can be configured to attach the stacked array to a host printed circuit board. The interposer can insulate the components from one another and also couple signals between the components on the first and second layers. In one embodiment, the components in the first and second layers are passive components.
    Type: Application
    Filed: August 27, 2012
    Publication date: August 8, 2013
    Applicant: Apple Inc.
    Inventors: Shawn X. ARNOLD, Douglas P. Kidd, Sean A. Mayo, Scott P. Mullins, Dennis R. Pyper, Jeffrey M. Thoma, Kenyu Tojima
  • Publication number: 20130197850
    Abstract: A device under test (DUT) may be tested using a radio-frequency test station. The DUT may include at least one antenna, wireless communications circuitry associated with the antenna, and other peripheral components such as a camera module, a display module, and audio circuitry. The test station may include a shielded enclosure in which the DUT is placed during testing. The DUT need not be electrically wired to any test equipment. The DUT may be configured to operate in self test mode. The DUT may be configured to obtain baseline noise floor measurements while all the peripheral components are deactivated and may be configured to obtain elevated noise floor measurements while selectively activating desired subsets of the peripheral components. The difference between the elevated and baseline noise floor measurements may be computed to determine whether at least some of the peripheral components negatively impact the antenna performance by an excessive amount.
    Type: Application
    Filed: January 26, 2012
    Publication date: August 1, 2013
    Inventors: Qishan Yu, Jeffrey M. Thoma, Robert S. Sorensen
  • Patent number: 8072356
    Abstract: Methods and apparatus for determining the operating states of a plurality of capacitive sensing buttons in a capacitive sensing user interface are disclosed. The capacitive sensing buttons are sampled in a round-robin fashion such that the decay time samples for the buttons are acquired in an interleaved manner during each sampling cycle. Provisions are made to reduce the initialization delay, to reduce transient-induced errors, and to obtain the operating states based on updated decay data samples for the buttons.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: December 6, 2011
    Assignee: Kyocera Corporation
    Inventors: John P. Taylor, Jeffrey M. Thoma
  • Patent number: 8029187
    Abstract: A temperature measuring and identification (TMID) device obtains identification information and temperature information of a connected device having a temperature sensing circuit (TSC). The TSC includes a temperature sensing element (TSE) connected in parallel with a voltage clamping network (VCN) that limits the voltage across the TSE to an identification voltage within an identification voltage range when the voltage is greater than or equal to a lower voltage of the identification voltage range. When a voltage below the lower range is applied to the TSC, the VCN appears as an open circuit and the resistance of the TSC corresponds to temperature. A translation circuit within the TMID shifts TSC voltages within the identification voltage range to a normalization voltage range. Accordingly, voltages corresponding to temperature as well as voltages corresponding to identification are within the normalization voltage range.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: October 4, 2011
    Assignee: Kyocera Corporation
    Inventors: John P. Taylor, Jeffrey M. Thoma
  • Publication number: 20100277351
    Abstract: Methods and apparatus for determining the operating states of a plurality of capacitive sensing buttons in a capacitive sensing user interface are disclosed. The capacitive sensing buttons are sampled in a round-robin fashion such that the decay time samples for the buttons are acquired in an interleaved manner during each sampling cycle. Provisions are made to reduce the initialization delay, to reduce transient-induced errors, and to obtain the operating states based on updated decay data samples for the buttons.
    Type: Application
    Filed: December 13, 2007
    Publication date: November 4, 2010
    Inventors: John P. TAYLOR, Jeffrey M. THOMA
  • Patent number: 7755412
    Abstract: The present example provides a circuit offering interoperability between circuits that may be powered from differing voltages, and that may operate at differing logic levels. Isolation may be provided from the impedance provided by transistor circuits and level shifting may be provided by a divider network. Accordingly, an exemplary slave and a master (or equivalently two circuits which are being coupled together) can operate on different voltages. This may be useful because some circuits such as processors can require higher or lower voltage than other processors that are sought to be coupled together. The circuit also may require one “read only” and another “input/output” pin, therefore, reducing the resources needed to implement the circuit functions. The present example can be useful for microprocessors that can use a software algorithm for the communications protocol, which can be economical to implement as it utilizes one input/output pin and one input only pin.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: July 13, 2010
    Assignee: Kyocera Corporation
    Inventor: Jeffrey M. Thoma
  • Patent number: 7752365
    Abstract: A bi-directional single conductor interrupt line is used in conjunction with a master only initiated data communication bus, to allow a slave device to submit a slave service request to a master device and to acknowledge master service requests from the master device. When not submitting a master service request, the master device maintains an interrupt line voltage at an idle state voltage by setting the interrupt line voltage through a pull resistor. The slave and master devices submit service requests by respectively driving or pulling the interrupt line voltage from the idle voltage to the service request voltage. The slave responds to a master service request or initiates the master servicing of a slave service request by subsequently driving the interrupt line back to the idle state voltage giving a slower slave ample time to prepare for a pending master initiated data transaction.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: July 6, 2010
    Assignee: Kyocera Corporation
    Inventors: John P. Taylor, Jeffrey M. Thoma
  • Publication number: 20090243695
    Abstract: The present example provides a circuit offering interoperability between circuits that may be powered from differing voltages, and that may operate at differing logic levels. Isolation may be provided from the impedance provided by transistor circuits and level shifting may be provided by a divider network. Accordingly, an exemplary slave and a master (or equivalently two circuits which are being coupled together) can operate on different voltages. This may be useful because some circuits such as processors can require higher or lower voltage than other processors that are sought to be coupled together. The circuit also may require one “read only” and another “input/output” pin, therefore, reducing the resources needed to implement the circuit functions. The present example can be useful for microprocessors that can use a software algorithm for the communications protocol, which can be economical to implement as it utilizes one input/output pin and one input only pin.
    Type: Application
    Filed: April 1, 2008
    Publication date: October 1, 2009
    Inventor: Jeffrey M. THOMA
  • Publication number: 20090248932
    Abstract: A bi-directional single conductor interrupt line is used in conjunction with a master only initiated data communication bus, to allow a slave device to submit a slave service request to a master device and to acknowledge master service requests from the master device. When not submitting a master service request, the master device maintains an interrupt line voltage at an idle state voltage by setting the interrupt line voltage through a pull resistor. The slave and master devices submit service requests by respectively driving or pulling the interrupt line voltage from the idle voltage to the service request voltage. The slave responds to a master service request or initiates the master servicing of a slave service request by subsequently driving the interrupt line back to the idle state voltage giving a slower slave ample time to prepare for a pending master initiated data transaction.
    Type: Application
    Filed: April 1, 2008
    Publication date: October 1, 2009
    Inventors: John P. Taylor, Jeffrey M. Thoma
  • Publication number: 20090014309
    Abstract: An apparatus, system, and method that initialize a capacitive sensing switch and detects a pushed button are described. The apparatus comprises a keypad, a logic component, an initialization threshold, a measured capacitive value, and a processor. The keypad is disposed on the wireless device and comprises at least one capacitive sensing switch. The logic component is configured to determine a capacitive sensing range for each capacitive sensing switch, wherein the capacitive sensing range corresponds to the difference between the maximum capacitance and the minimum capacitance. The initialization threshold is associated with the capacitive sensing range and each capacitive sensing switch is initialized when the capacitive sensing range exceeds the initialization threshold. The measured capacitive value measures the capacitive value for each capacitive sensing switch and a corresponding push-button threshold determines whether the button has been pushed.
    Type: Application
    Filed: July 11, 2007
    Publication date: January 15, 2009
    Inventor: Jeffrey M. THOMA
  • Publication number: 20080198898
    Abstract: A temperature measuring and identification (TMID) device obtains identification information and temperature information of a connected device having a temperature sensing circuit (TSC). The TSC includes a temperature sensing element (TSE) connected in parallel with a voltage clamping network (VCN) that limits the voltage across the TSE to an identification voltage within an identification voltage range when the voltage is greater than or equal to a lower voltage of the identification voltage range. When a voltage below the lower range is applied to the TSC, the VCN appears as an open circuit and the resistance of the TSC corresponds to temperature. A translation circuit within the TMID shifts TSC voltages within the identification voltage range to a normalization voltage range. Accordingly, voltages corresponding to temperature as well as voltages corresponding to identification are within the normalization voltage range.
    Type: Application
    Filed: February 21, 2007
    Publication date: August 21, 2008
    Inventors: John P. Taylor, Jeffrey M. Thoma