Abstract: Exemplary embodiments are directed to systems and methods for controlling an outlet temperature of an evaporator having a plurality of evaporator tube bundles, in which a processor is configured to compute an outlet temperature setpoint for the evaporator based on outlet temperatures of each of the plurality of evaporator tube bundles. The processor also regulates fluid flow through at least one of the evaporator tube bundles to reduce deviation between the outlet temperature of the evaporator and the outlet temperature setpoint for the evaporator.

Abstract: Exemplary embodiments are directed to systems and methods for controlling an outlet temperature of an evaporator having a plurality of evaporator tube bundles, in which a processor is configured to compute an outlet temperature setpoint for the evaporator based on outlet temperatures of each of the plurality of evaporator tube bundles. The processor also regulates fluid flow through at least one of the evaporator tube bundles to reduce deviation between the outlet temperature of the evaporator and the outlet temperature setpoint for the evaporator.

Abstract: A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.

Abstract: A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the worst-case set-up time. The select signal to the multiplexer is delayed sufficiently to compensate for non-uniformity of duty cycle of data at the inputs to the multiplexer. Compensation of the non-uniformity allows the data on the wire to have a uniform duty cycle for all data transferred regardless of which latch is sourcing the data. The multiplexer that selects data from the two latches which are launching data on the edge of different clocks has a select line that is delayed by a variable amount to tune the select such that the data is clean at the input to the multiplexer on all ports.

Abstract: A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.

Abstract: A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the worst-case set-up time. The select signal to the multiplexer is delayed sufficiently to compensate for non-uniformity of duty cycle of data at the inputs to the multiplexer. Compensation of the non-uniformity allows the data on the wire to have a uniform duty cycle for all data transferred regardless of which latch is sourcing the data. The multiplexer that selects data from the two latches which are launching data on the edge of different clocks has a select line that is delayed by a variable amount to tune the select such that the data is clean at the input to the multiplexer on all ports.

Abstract: Cryptographic functions are implemented in execution unit hardware on the CPU of a computer system. This implementation enables a lower latency for calling and executing cryptographic operations and increases the efficiency. This decreased latency greatly enhances the capability of general purpose processors in systems that frequently do many cryptographic operations, particularly when only small amounts of data are involved. This allows an implementation that can significantly accelerate the processes involved in doing secure online transactions.