Patents by Inventor Jeffrey McKeveny
Jeffrey McKeveny has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7070909Abstract: The glass transmittance of UV light having a wavelength of 365 nanometers is reduced by compounding an oxide or salt of at least one of Fe, Cu, Cr, Ce, Mn and mixtures thereof. The fiberglass cloth can be used for providing reinforced prepregs used in producing printed circuit boards or laminated chip carrier substrates.Type: GrantFiled: August 30, 2004Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Robert M. Japp, Pamela Lulkoski, Jeffrey McKeveny, Jan Obrzut, Kenneth Lynn Potter
-
Patent number: 7007378Abstract: A process for manufacturing a land grid array connector for a printed wiring board is disclosed. The process does not require electroplating precious metal overlays. Therefore, no commoning bar is required. Another benefit of the invention includes a connector design using only a flash, soft gold application in the outer surface of the connector. Physical hardness and durability are derived from a thin palladium layer lying beneath the flash gold layer.Type: GrantFiled: December 12, 2002Date of Patent: March 7, 2006Assignee: International Business Machines CorporationInventors: John G. Gaudiello, James D. Herard, John J. Konrad, Jeffrey McKeveny, Timothy L. Wells
-
Patent number: 6931722Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.Type: GrantFiled: March 24, 2003Date of Patent: August 23, 2005Assignee: International Business Machines CorporationInventors: Edward L. Arrington, Anilkumar C. Bhatt, Edmond O. Fey, Kevin T. Knadle, John J. Konrad, Joseph A Kotylo, Jeffrey McKeveny, Jose A. Rios, Amit K. Sarkhel, Andrew M. Seman, Timothy L. Wells
-
Patent number: 6919514Abstract: Embedded flush circuitry features are provided by providing a conductive seed layer on the sidewalls and bottom of laser ablated trench features plating a layer of conductive metal onto the seed layer and depositing a layer of dielectric material.Type: GrantFiled: September 15, 2003Date of Patent: July 19, 2005Assignee: International Business Machines CorporationInventors: John Joseph Konrad, Jeffrey McKeveny, James Warren Wilson
-
Publication number: 20050026051Abstract: The glass transmittance of UV light having a wavelength of 365 nanometers is reduced by compounding an oxide or salt of at least one of Fe, Cu, Cr, Ce, Mn and mixtures thereof. The fiberglass cloth can be used for providing reinforced prepregs used in producing printed circuit boards or laminated chip carrier substrates.Type: ApplicationFiled: August 30, 2004Publication date: February 3, 2005Applicant: International Business Machines CorporationInventors: Robert Japp, Pamela Lulkoski, Jeffrey McKeveny, Jan Obrzut, Kenneth Potter
-
Patent number: 6838400Abstract: The glass transmittance of UV light having a wavelength of 365 nanometers is reduced by compounding an oxide or salt of at least one of Fe, Cu, Cr, Ce, Mn and mixtures thereof. The fiberglass cloth can be used for providing reinforced prepregs used in producing printed circuit boards or laminated chip carrier substrates.Type: GrantFiled: March 23, 1998Date of Patent: January 4, 2005Assignee: International Business Machines CorporationInventors: Robert Maynard Japp, Pamela Lulkoski, Jeffrey McKeveny, Jan Obrzut, Kenneth Lynn Potter
-
Patent number: 6730857Abstract: Embedded flush circuitry features are fabricated by providing a conductive seed layer on the sidewalls and bottom of laser ablated trench features plating a layer of conductive metal onto the seed layer and depositing a later of dielectric material.Type: GrantFiled: March 13, 2001Date of Patent: May 4, 2004Assignee: International Business Machines CorporationInventors: John Joseph Konrad, Jeffrey McKeveny, James Warren Wilson
-
Publication number: 20040064939Abstract: Embedded flush circuitry features are provided by providing a conductive seed layer on the sidewalls and bottom of laser ablated trench features plating a layer of conductive metal onto the seed layer and depositing a layer of dielectric material.Type: ApplicationFiled: September 15, 2003Publication date: April 8, 2004Applicant: International Business Machines CorporationInventors: John Joseph Konrad, Jeffrey McKeveny, James Warren Wilson
-
Publication number: 20030177635Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.Type: ApplicationFiled: March 24, 2003Publication date: September 25, 2003Inventors: Edward L. Arrington, Anilkumar C. Bhatt, Edmond O. Fey, Kevin T. Knadle, John J. Konrad, Joseph A. Kotylo, Jeffrey McKeveny, Jose A. Rios, Amit K. Sarkhel, Andrew M. Seman, Timothy L. Wells
-
Patent number: 6586683Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.Type: GrantFiled: April 27, 2001Date of Patent: July 1, 2003Assignee: International Business Machines CorporationInventors: Edward L. Arrington, Anilkumar C. Bhatt, Edmond O. Fey, Kevin T. Knadle, John J. Konrad, Joseph A. Kotylo, Jeffrey McKeveny, Jose A. Rios, Amit K. Sarkhel, Andrew M. Seman, Timothy L. Wells
-
Publication number: 20030102160Abstract: A process for manufacturing a land grid array connector for a printed wiring board is disclosed. The process does not require electroplating precious metal overlays. Therefore, no commoning bar is required. Another benefit of the invention includes a connector design using only a flash, soft gold application in the outer surface of the connector. Physical hardness and durability are derived from a thin palladium layer lying beneath the flash gold layer.Type: ApplicationFiled: December 12, 2002Publication date: June 5, 2003Applicant: International Business Machines CorporationInventors: John G. Gaudiello, James D. Herard, John J. Konrad, Jeffrey McKeveny, Timothy L. Wells
-
Patent number: 6485892Abstract: Through-holes in a substrate are masked during plating of the substrate by substantially filling the through-holes with a liquid material, followed by applying a photoimageable material to an external surface of the substrate, forming a predetermined pattern in the photoimageable material, circuitizing the predetermined pattern and then removing both the photoimageable material and the liquid material from the through-holes.Type: GrantFiled: December 17, 1999Date of Patent: November 26, 2002Assignee: International Business Machines CorporationInventors: Lawrence Robert Blumberg, Norman A. Card, Jr., Richard Allen Day, Stephen J. Fuerniss, John Joseph Konrad, Jeffrey McKeveny, Timothy L. Wells
-
Publication number: 20020157861Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.Type: ApplicationFiled: April 27, 2001Publication date: October 31, 2002Applicant: International Business Machines CorporationInventors: Edward L. Arrington, Anilkumar C. Bhatt, Edmond O. Fey, Kevin T. Knadle, John J. Konrad, Joseph A. Kotylo, Jeffrey McKeveny, Jose A. Rios, Amit K. Sarkhel, Andrew M. Seman, Timothy L. Wells
-
Publication number: 20020129972Abstract: Embedded flush circuitry features are provided by providing a conductive seed layer on the sidewalls and bottom of laser ablated trench features plating a layer of conductive metal onto the seed layer and depositing a layer of dielectric material.Type: ApplicationFiled: March 13, 2001Publication date: September 19, 2002Applicant: International Business Machines CorporationInventors: John Joseph Konrad, Jeffrey McKeveny, James Warren Wilson
-
Patent number: 6025057Abstract: A method of fabricating an electronic package having an organic substrate. The substrate is formed of fiberglass and epoxy. In order to additively circuitize the electronic package substrate, an organic polyelectrolyte is deposited onto the organic substrate. A colloidal palladium-tin seed layer is deposited atop the organic polyelectrolyte. This is followed by depositing a photoimageable polymer atop the seed layer, and photolithographically patterning the photoimageable polymer to uncover portions of the seed. layer. The uncovered portions of the seed layer are catalytic to the electroless deposition of copper. In this way a conductive layer of copper is deposited atop the uncovered seed layer. The organic polyelectrolyte is deposited from an aqueous solution at the pH appropriate for the desired seed catalyst coating, depending on the ionizable character of the particular polyelectrolyte employed.Type: GrantFiled: December 17, 1997Date of Patent: February 15, 2000Assignee: International Business Machines CorporationInventors: Anastasios Peter Angelopoulos, Gerald Walter Jones, Richard William Malek, Heike Marcello, Jeffrey McKeveny
-
Patent number: 5866237Abstract: A method of fabricating an electronic package having an organic substrate. The substrate is formed of fiberglass and epoxy. In order to additively circuitize the electronic package substrate, an organic polyelectrolyte is deposited onto the organic substrate. A colloidal palladium-tin seed layer is deposited atop the organic polyelectrolyte. This is followed by depositing a photoimagable polymer atop the seed layer, and photolithographically patterning the photoimagable polymer to uncover portions of the seed layer. The uncovered portions of the seed layer are catalytic to the electroless deposition of copper. In this way a conductive layer of copper is deposited atop the uncovered seed layer. The organic polyelectrolyte is deposited from an aqueous solution at the pH appropriate for the desired seed catalyst coating, depending on the ionizable character of the particular polyelectrolyte employed.Type: GrantFiled: August 23, 1996Date of Patent: February 2, 1999Assignee: International Business Machines CorporationInventors: Anastasios Peter Angelopoulos, Gerald Walter Jones, Richard William Malek, Heike Marcello, Jeffrey McKeveny
-
Patent number: 5599747Abstract: A method of making a circuitized substrate which may be utilized as a chip carrier structure. The method involves the steps of providing a dielectric member and partially routing this member to define a temporary support portion therein. Metallization and circuitization may then occur, following which the temporary support portion is removed. This temporary support thus assures effective support for the photoresist used as part of the circuitization process. Thus, the photoresist is capable of being applied in sheetlike form for spanning the relatively small openings of the dielectric without sagging, bowing, etc., which may adversely impact subsequent processing steps.Type: GrantFiled: June 27, 1995Date of Patent: February 4, 1997Assignee: International Business Machines CorporationInventors: Ashwinkumar C. Bhatt, Thomas P. Duffy, David E. Houser, Gerald W. Jones, Jeffrey McKeveny, Kenneth L. Potter
-
Patent number: 5578796Abstract: According to the present invention, a method of laminating at least two substrates together and circuitizing at least one surface of the laminate is provided. Pressure is exerted against opposite surfaces of each of said two substrates. An opening extends from a circuit-receiving surface of at least one of said substrates. A plug is provided which is configured to removably fit into said opening and has a support surface thereon which is substantially coplanar with the circuit-receiving surface when said plug is positioned in the opening. The plug is inserted in the opening with the support surface substantially coplanar with the circuit-receiving surface. The substrates are laminated by application of pressure on the opposite surfaces of the substrates. The circuit-receiving surface and the support surface are covered with a sheet of dry film photoresist to seal around the opening with said plug member supporting said sheet of photoresist in the region of the opening.Type: GrantFiled: June 6, 1995Date of Patent: November 26, 1996Assignee: International Business Machines CorporationInventors: Ashwinkumar C. Bhatt, Thomas P. Duffy, Gerry A. Hackett, Jeffrey McKeveny
-
Patent number: 5542175Abstract: According to the present invention, a method of laminating at least two substrates together and circuitizing at least one surface of the laminate is provided. Pressure is exerted against opposite surfaces of each of said two substrates. An opening extends from a circuit-receiving surface of at least one of said substrates. A plug is provided which is configured to removably fit into said opening and has a support surface thereon which is substantially coplanar with the circuit-receiving surface when said plug is positioned in the opening. The plug is inserted in the opening with the support surface substantially coplanar with the circuit-receiving surface. The substrates are laminated by application of pressure on the opposite surfaces of the substrates. The circuit-receiving surface and the support surface are covered with a sheet of dry film photoresist to seal around the opening with said plug member supporting said sheet of photoresist in the region of the opening.Type: GrantFiled: December 20, 1994Date of Patent: August 6, 1996Assignee: International Business Machines CorporationInventors: Ashwinkumar C. Bhatt, Thomas P. Duffy, Gerry A. Hackett, Jeffrey McKeveny
-
Patent number: 5229550Abstract: A structure and method are disclosed for making high density circuit board. Using photosensitive or other dielectric materials over a circuitized power core, vias and lands are opened up, filled with joining metal and aligned with the next level, eliminating a major registration problem in building up a high density composite and reducing the number of steps in the manufacturing process.Type: GrantFiled: March 31, 1992Date of Patent: July 20, 1993Assignee: International Business Machines CorporationInventors: Perminder S. Bindra, Dennis A. Canfield, Voya Rista Markovich, Jeffrey McKeveny, Robert E. Ruane, Edwin L. Thomas