Abstract: Apparatuses and methods for providing and interpreting command packets for direct control of memory channels are disclosed herein. An example apparatus includes flash memories configured into channels and a controller coupled to the flash memories. The controller receives packets and interpret the packets based at least on a first protocol, and determines whether any packets are linked based on a link identifier included in a block of each packet. The controller arranges the subset of packets based on an index included in the block of each packet of the subset of packets, and the subset of packets are arranged in order based on the respective indexes. A target flash memory and a target channel are determined by the controller based on flash memory and channel identifiers included in the block of each of the packet of the subset of packets.

Abstract: Apparatuses and methods for providing and interpreting command packets for direct control of memory channels are disclosed herein. An example apparatus includes flash memories configured into channels and a controller coupled to the flash memories. The controller receives packets and interpret the packets based at least on a first protocol, and determines whether any packets are linked based on a link identifier included in a block of each packet. The controller arranges the subset of packets based on an index included in the block of each packet of the subset of packets, and the subset of packets are arranged in order based on the respective indexes. A target flash memory and a target channel are determined by the controller based on flash memory and channel identifiers included in the block of each of the packet of the subset of packets.

Abstract: Apparatuses and methods for providing and interpreting command packets for direct control of memory channels are disclosed herein. An example apparatus includes flash memories configured into channels and a controller coupled to the flash memories. The controller receives packets and interpret the packets based at least on a first protocol, and determines whether any packets are linked based on a link identifier included in a block of each packet. The controller arranges the subset of packets based on an index included in the block of each packet of the subset of packets, and the subset of packets are arranged in order based on the respective indexes. A target flash memory and a target channel are determined by the controller based on flash memory and channel identifiers included in the block of each of the packet of the subset of packets.

Abstract: An embodiment of a semiconductor apparatus may include technology to provide information related to one or more parity capabilities of a controller and a persistent storage media in response to an inquiry from a host device, and adjust one or more parameters related to the one or more parity capabilities of the controller and the persistent storage media in response to a request from the host device. Other embodiments are disclosed and claimed.

Abstract: Apparatuses and methods for providing and interpreting command packets for the direct control of non-volatile memory channels within a solid state drive are disclosed herein. An example apparatus may include a plurality of flash memories configured into a plurality of channels and a controller coupled to the plurality of flash memories.

Abstract: Apparatuses and methods for providing and intetpreting command packets for direct control of memory channels are disclosed herein. An example apparatus includes flash memories configured into channels and a controller coupled to the flash memories. The controller receives packets and interpret the packets based at least on a first protocol, and determines whether any packets are linked based on a link identifier included in a block of each packet. The controller arranges the subset of packets based on an index included in the block of each packet of the subset of packets, and the subset of packets are arranged in order based on the respective indexes. A target flash memory and a target channel are determined by the controller based on flash memory and channel identifiers included in the block of each of the packet of the subset of packets.

Abstract: An embodiment of a semiconductor apparatus may include technology to provide information related to one or more parity capabilities of a controller and a persistent storage media in response to an inquiry from a host device, and adjust one or more parameters related to the one or more parity capabilities of the controller and the persistent storage media in response to a request from the host device. Other embodiments are disclosed and claimed.

Abstract: Some embodiments include apparatuses and methods having memory cells and a control unit. The control unit can retrieve information from a first portion of the memory cells. The information can include bits organized into a first bit group and second bit group. The information can be associated with management information. The control unit can store the first and second bits in the second group in a second portion of the memory cells. The control unit can update the first and second management information after the second bit group is stored.

Abstract: Apparatuses and methods for providing and interpreting command packets for the direct control of non-volatile memory channels within a solid state drive are disclosed herein. An example apparatus may include a plurality of flash memories configured into a plurality of channels and a controller coupled to the plurality of flash memories.

Abstract: Some embodiments include apparatuses and methods having memory cells and a control unit. The control unit can retrieve information from a first portion of the memory cells. The information can include bits organized into a first bit group and second bit group. The information can be associated with management information. The control unit can store the first and second bits in the second group in a second portion of the memory cells. The control unit can update the first and second management information after the second bit group is stored.

Abstract: The present disclosure is related to apparatuses operable in multiple power modes and methods of operating the same. An example embodiment includes an apparatus comprising a memory comprising an array of memory cells operable to store single-level cell (SLC) data and multi-level cell (MLC) data. The apparatus can include a controller coupled to the memory and configured to: responsive to the apparatus being in a first power mode, fold SLC data into MLC data; and prevent SLC data from being folded into MLC data responsive to the apparatus being in a second power mode.

Abstract: In some embodiments, a mass storage system may include a mass storage device having a plurality of memory channels, and a controller coupled to the mass storage device, wherein the controller is configured to control access to the mass storage device. For example, the controller may include code to determine a first vertical redirect budget for a first memory channel of the plurality of memory channels, revector defects in the first memory channel vertically within the first memory channel until the first vertical redirect budget is exceeded, and revector defects in the first memory channel horizontally outside of the first memory channel within another memory channel of the plurality of memory channels after the first vertical redirect budget is exceeded. Other embodiments are disclosed and claimed.

Abstract: In some embodiments, a mass storage system may include a mass storage device having a plurality of memory channels, and a controller coupled to the mass storage device, wherein the controller is configured to control access to the mass storage device. For example, the controller may include code to determine a first vertical redirect budget for a first memory channel of the plurality of memory channels, revector defects in the first memory channel vertically within the first memory channel until the first vertical redirect budget is exceeded, and revector defects in the first memory channel horizontally outside of the first memory channel within another memory channel of the plurality of memory channels after the first vertical redirect budget is exceeded. Other embodiments are disclosed and claimed.