Patents by Inventor Jeffrey Milton
Jeffrey Milton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8331180Abstract: A static random access memory (SRAM) includes an SRAM cell to store a bit of data. A word line accesses the SRAM cell, which, responsively, during a read, drives either a bit line true (BLT) or a bit line complement (BLC) low. Both BLT and BLC are precharged to a supply voltage, then, subsequently are discharged to a reference voltage, lower than the supply voltage, prior to the word line being activated. Because the bit lines are at a voltage lower than the supply voltage when the SRAM cell is activated, the SRAM cell stability is improved.Type: GrantFiled: September 30, 2010Date of Patent: December 11, 2012Assignee: International Business Machines CorporationInventors: Chad Allen Adams, Sharon Huertas Cesky, Elizabeth Lair Gerhard, Jeffrey Milton Scherer
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Patent number: 8213249Abstract: A method and static random access memory (SRAM) circuit for implementing low power data predicting local evaluation for double pumped arrays, and a design structure on which the subject circuit reside are provided. A novel variation of a domino read local evaluation circuit accurately predicts the write data for the next cycle. The domino read local evaluation circuit uses static write data set up prior to a write enable signal to determine the value of the data that is being written into the array. When the data being written to the array matches the data last read the local bitlines stay in their previous state. When the data being written is opposite of the data last read then the bit lines are precharged to the precharge value.Type: GrantFiled: May 27, 2010Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Chad Allen Adams, Sharon Huertas Cesky, Elizabeth Lair Gerhard, Jeffrey Milton Scherer
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Publication number: 20120081949Abstract: A static random access memory (SRAM) includes an SRAM cell to store a bit of data. A word line accesses the SRAM cell, which, responsively, during a read, drives either a bit line true (BLT) or a bit line complement (BLC) low. Both BLT and BLC are precharged to a supply voltage, then, subsequently are discharged to a reference voltage, lower than the supply voltage, prior to the word line being activated. Because the bit lines are at a voltage lower than the supply voltage when the SRAM cell is activated, the SRAM cell stability is improved.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chad Allen Adams, Sharon Huertas Cesky, Elizabeth Lair Gerhard, Jeffrey Milton Scherer
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Publication number: 20110292748Abstract: A method and static random access memory (SRAM) circuit for implementing low power data predicting local evaluation for double pumped arrays, and a design structure on which the subject circuit reside are provided. A novel variation of a domino read local evaluation circuit accurately predicts the write data for the next cycle. The domino read local evaluation circuit uses static write data set up prior to a write enable signal to determine the value of the data that is being written into the array. When the data being written to the array matches the data last read the local bitlines stay in their previous state. When the data being written is opposite of the data last read then the bit lines are precharged to the precharge value.Type: ApplicationFiled: May 27, 2010Publication date: December 1, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chad Allen Adams, Sharon Huertas Cesky, Elizabeth Lair Gerhard, Jeffrey Milton Scherer
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Patent number: 7783943Abstract: A method and apparatus for testing a random access memory device is provided. One embodiment involves providing an interface between Logic Built in Self Test (LBIST) and Array Built in Self Test (ABIST) paths for memory testing, including providing a cross-coupled NAND device with an LBIST test path; configuring the cross-coupled NAND device for interfacing ABIST and LBIST paths by modeling a worst case scenario for timing from a domino read static random access memory (SRAM) array; and modifying data in the cross-coupled NAND device using an LBIST controlled data path at essentially the latest point in time when a read may propagate from the array to provide full AC test coverage of down stream logic.Type: GrantFiled: May 15, 2008Date of Patent: August 24, 2010Assignee: International Business Machines CorporationInventors: Chad Allen Adams, Elizabeth Lair Gerhard, Sharon Huertas Cesky, Jeffrey Milton Scherer
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Patent number: 7751266Abstract: A design structure embodied in a machine readable medium used in a design process and an integrated circuit for high performance SRAM (Static Random Access Memory) read bypass for BIST (built-in self-test). The design structure and integrated structure includes a dynamic to static conversion unit for a read output of an SRAM array, and a test bypass unit integrated into the dynamic to static conversion unit, so as to allow the read output of the SRAM array to pass through in a non-test mode without impacting performance, and bypass the read output of the SRAM array and allow a test signal to pass though in a test mode.Type: GrantFiled: June 26, 2008Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Chad Allen Adams, Derick Gardner Behrends, Daniel Mark Nelson, Jeffrey Milton Scherer
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Publication number: 20090323445Abstract: A design structure embodied in a machine readable medium used in a design process and an integrated circuit for high performance SRAM (Static Random Access Memory) read bypass for BIST (built-in self-test). The design structure and integrated structure includes a dynamic to static conversion unit for a read output of an SRAM array, and a test bypass unit integrated into the dynamic to static conversion unit, so as to allow the read output of the SRAM array to pass through in a non-test mode without impacting performance, and bypass the read output of the SRAM array and allow a test signal to pass though in a test mode.Type: ApplicationFiled: June 26, 2008Publication date: December 31, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chad Allen Adams, Derick Gardner Behrends, Daniel Mark Nelson, Jeffrey Milton Scherer
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Publication number: 20090285039Abstract: A method and apparatus for write assist for a static random access memory (SRAM) array, is provided, which increases the write ability of the SRAM cell by locally raising the source voltage. One embodiment involves locally generating a virtual ground for write assist on column selected SRAM cells, including locally raising the source voltage to increase the write ability of the SRAM cell; wherein locally raising the source voltage comprises locally generating a virtual source/ground node for boosting the write ability of a column of SRAM cells without using an additional on-chip or off-chip supply; thereby decreasing the voltage differential across the source and supply of the column of SRAM cells during a write, and restoring the standard chip differential during a read.Type: ApplicationFiled: May 15, 2008Publication date: November 19, 2009Applicant: International Business Machines CorporationInventors: Chad Allen Adams, Elizabeth Lair Gerhard, Sharon Huertas Cesky, Jeffrey Milton Scherer
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Publication number: 20090287971Abstract: A method and apparatus for testing a random access memory device is provided. One embodiment involves providing an interface between Logic Built in Self Test (LBIST) and Array Built in Self Test (ABIST) paths for memory testing, including providing a cross-coupled NAND device with an LBIST test path; configuring the cross-coupled NAND device for interfacing ABIST and LBIST paths by modeling a worst case scenario for timing from a domino read static random access memory (SRAM) array; and modifying data in the cross-coupled NAND device using an LBIST controlled data path at essentially the latest point in time when a read may propagate from the array to provide full AC test coverage of down stream logic.Type: ApplicationFiled: May 15, 2008Publication date: November 19, 2009Applicant: International Business Machines CorporationInventors: Chad Allen Adams, Elizabeth Lair Gerhard, Sharon Huertas Cesky, Jeffrey Milton Scherer
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Patent number: 7409634Abstract: The system for end-to-end content publishing using XML with an object dependency graph is based on the following two design principles: First, separation of content and style: Information stored in the content management system is independent on how it is going to be presented. The presentation style is encapsulated elsewhere and can be used to customize the look and feel based on the end-user preferences as well as the delivery methods and devices. Second, reusability of information content: By encapsulating common information in fragments and subfragments and making these fragments insertable in other fragments, thereby avoid scattering and duplication of information. This enables a user to restrict the edit operations to a limited number of relevant fragments, to affect global changes. In addition, the present invention provides data consistency and data integrity in the content management.Type: GrantFiled: July 26, 2006Date of Patent: August 5, 2008Assignee: International Business Machines CorporationInventors: Peter E. Davis, Sara Elo Dean, Dikran S. Meliksetian, Jeffrey Milton, Louis Weitzman, Nianjun Zhou
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Publication number: 20060294459Abstract: The system for end-to-end content publishing using XML with an object dependency graph is based on the following two design principles: First, separation of content and style: Information stored in the content management system is independent on how it is going to be presented. The presentation style is encapsulated elsewhere and can be used to customize the look and feel based on the end-user preferences as well as the delivery methods and devices. Second, reusability of information content: By encapsulating common information in fragments and subfragments and making these fragments insertable in other fragments, thereby avoid scattering and duplication of information. This enables a user to restrict the edit operations to a limited number of relevant fragments, to affect global changes. In addition, the present invention provides data consistency and data integrity in the content management.Type: ApplicationFiled: July 26, 2006Publication date: December 28, 2006Applicant: International Business Machines CorporationInventors: Peter Davis, Sara Elo Dean, Dikran Meliksetian, Jeffrey Milton, Louis Weitzman, Nianjun Zhou
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Publication number: 20060230271Abstract: A method and system provide digital certificates of authentication for authenticating software installed on computer devices. The digital certificates of authentication authorized the use of software installed on computer devices by binding such a digital certificate to an attribute of the computer device. In one example, the digital certificate of authentication is bound to a motherboard serial number of a computer device. The method and system further provide a secure environment for transmitting one or more digital certificates of authentication.Type: ApplicationFiled: March 30, 2005Publication date: October 12, 2006Applicant: Microsoft CorporationInventors: Jeffrey Milton, Albert Buckingham, Krishnakumar Sethuraman, Stephanie Herndon
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Patent number: 7076728Abstract: The system for end-to-end content publishing using XML with an object dependency graph is based on the following two design principles: First, separation of content and style: Information stored in the content management system is independent on how it is going to be presented. The presentation style is encapsulated elsewhere and can be used to customize the look and feel based on the end-user preferences as well as the delivery methods and devices. Second, reusability of information content: By encapsulating common information in fragments and subfragments and making these fragments insertable in other fragments, thereby avoid scattering and duplication of information. This enables a user to restrict the edit operations to a limited number of relevant fragments, to affect global changes. In addition, the present invention provides data consistency and data integrity in the content management.Type: GrantFiled: December 22, 2000Date of Patent: July 11, 2006Assignee: International Business Machines CorporationInventors: Peter E. Davis, Sara Elo Dean, Dikran S. Meliksetian, Jeffrey Milton, Louis Weitzman, Nianjun Zhou
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Publication number: 20020133516Abstract: The system for end-to-end content publishing using XML with an object dependency graph is based on the following two design principles: First, separation of content and style: Information stored in the content management system is independent on how it is going to be presented. The presentation style is encapsulated elsewhere and can be used to customize the look and feel based on the end-user preferences as well as the delivery methods and devices. Second, reusability of information content: By encapsulating common information in fragments and subfragments and making these fragments insertable in other fragments, thereby avoid scattering and duplication of information. This enables a user to restrict the edit operations to a limited number of relevant fragments, to affect global changes. In addition, the present invention provides data consistency and data integrity in the content management.Type: ApplicationFiled: December 22, 2000Publication date: September 19, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter E. Davis, Sara Elo Dean, Dikran S. Meliksetian, Jeffrey Milton, Louis Weitzman, Nianjun Zhou