Abstract: A processing device of a memory sub-system is configured to receive, from a host system, host data to be stored at a memory sub-system in an encrypted form; determine that the host data exceeds a threshold size associated with an encryption operation; separate the host data into a plurality of segments based on the threshold size associated with the encryption operation; determine that a particular segment of the plurality of segments does not satisfy a size requirement of data associated with the encryption operation; modify the particular segment to satisfy the size requirement of data associated with the encryption operation; encrypt each of the plurality of segments based on the encryption operation; and store the encrypted plurality of segments at the memory sub-system.

Abstract: A processing device of a memory sub-system is configured to receive, from a host system, host data to be stored at a memory sub-system in an encrypted form; determine that the host data exceeds a threshold size associated with an encryption operation; separate the host data into a plurality of segments based on the threshold size associated with the encryption operation; determine that a particular segment of the plurality of segments does not satisfy a size requirement of data associated with the encryption operation; modify the particular segment to satisfy the size requirement of data associated with the encryption operation; encrypt each of the plurality of segments based on the encryption operation; and store the encrypted plurality of segments at the memory sub-system.

Abstract: Host data can be received at a memory sub-system. A determination can be made that the host data exceeds a threshold size associated with an encryption operation. The host data can be separated into segments based on the threshold size associated with the encryption operation. Each of the segments can be encrypted based on the encryption operation. Furthermore, the encrypted segments can be stored at the memory sub-system.

Abstract: A method includes compressing input data to form compressed data and comparing a size of the compressed data to a maximum allowed size determined from a fixed sector size for a lower tier of the multi-tier storage system and a minimum pad length for a pad that is stored in the same sector as the compressed data when the compressed data is migrated to the lower tier. When the size of the compressed data is greater than the maximum allowed size, the input data is stored instead of the compressed data in an upper tier of the multi-tier storage system.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

Abstract: Host data can be received at a memory sub-system. A determination can be made that the host data exceeds a threshold size associated with an encryption operation. The host data can be separated into segments based on the threshold size associated with the encryption operation. Each of the segments can be encrypted based on the encryption operation. Furthermore, the encrypted segments can be stored at the memory sub-system.

Abstract: Apparatus and method for managing namespaces in a Non-Volatile Memory Express (NVMe) controller environment. A non-volatile memory (NVM) is arranged to store map units (MUs) as addressable data blocks in one or more namespaces. A forward map has a sequence of map unit address (MUA) entries that correlate each of the MUs with the physical locations in the NVM. The MUA entries are grouped into immediately adjacent, contiguous ranges for each of the namespaces. A base MUA array identifies the address, within the forward map, of the beginning MUA entry for each namespace. A new namespace may be added by appending a new range of the MUA entries to the forward map immediate following the last MUA entry, and by adding a new entry to the base MUA array to identify the address, within the forward map, of the beginning MUA entry for the new namespace.

Abstract: A data storage device with one or more buffers can employ buffer tenure management with at least a data storage device having a first buffer, a second buffer, a buffer manager, and a non-volatile memory. The first buffer can be located on-chip while the second buffer is located off-chip. The first buffer may be filled with data having a tenure of less than a predetermined tenure threshold as directed by the buffer manager.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

Abstract: A method includes compressing input data to form compressed data and comparing a size of the compressed data to a maximum allowed size determined from a fixed sector size for a lower tier of the multi-tier storage system and a minimum pad length for a pad that is stored in the same sector as the compressed data when the compressed data is migrated to the lower tier. When the size of the compressed data is greater than the maximum allowed size, the input data is stored instead of the compressed data in an upper tier of the multi-tier storage system.

Abstract: A data storage device with one or more buffers can employ buffer tenure management with at least a data storage device having a first buffer, a second buffer, a buffer manager, and a non-volatile memory. The first buffer can be located on-chip while the second buffer is located off-chip. The first buffer may be filled with data having a tenure of less than a predetermined tenure threshold as directed by the buffer manager.

Abstract: A data storage device can be configured with a data map that has one or more custom map attributes. A non-volatile memory of the data storage device may store data organized into a data map by a mapping module. The data map consisting of at least a data address translation and a custom attribute pertaining to an operational parameter of the data map with the custom attribute generated and maintained by the mapping module.

Abstract: Apparatus and method for managing namespaces in a Non-Volatile Memory Express (NVMe) controller environment. A non-volatile memory (NVM) is arranged to store map units (MUs) as addressable data blocks in one or more namespaces. A forward map has a sequence of map unit address (MUA) entries that correlate each of the MUs with the physical locations in the NVM. The MUA entries are grouped into immediately adjacent, contiguous ranges for each of the namespaces. A base MUA array identifies the address, within the forward map, of the beginning MUA entry for each namespace. A new namespace may be added by appending a new range of the MUA entries to the forward map immediate following the last MUA entry, and by adding a new entry to the base MUA array to identify the address, within the forward map, of the beginning MUA entry for the new namespace.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

Abstract: Apparatus and method for managing map data in a data storage device. A programmable processor issues a find command to locate and place a requested map page of a map structure into a first cache to service a received host command. A non-programmable hardware circuit searches a forward table to determine whether the requested map page is in a second cache, and if so, loads the map page to the first cache. If not, the hardware circuit requests the requested map page from a back end processor which retrieves the requested map page from a non-volatile memory (NVM), such as a flash memory array. The hardware circuit searches a reverse table and the first cache to select a candidate location in the second cache for the retrieved requested map page from the NVM, and directs the storage of a copy of the requested map page at the candidate location.

Abstract: Apparatus and method for managing map data in a data storage device. A programmable processor issues a find command to locate and place a requested map page of a map structure into a first cache to service a received host command. A non-programmable hardware circuit searches a forward table to determine whether the requested map page is in a second cache, and if so, loads the map page to the first cache. If not, the hardware circuit requests the requested map page from a back end processor which retrieves the requested map page from a non-volatile memory (NVM), such as a flash memory array. The hardware circuit searches a reverse table and the first cache to select a candidate location in the second cache for the retrieved requested map page from the NVM, and directs the storage of a copy of the requested map page at the candidate location.