Abstract: A method of operating shared memory in a multiple processor system. A token is by default maintained with a first processor, the token enabling access to shared memory. A determination is made that a second processor requires access to shared memory. A determination is also made as to whether the first processor is accessing to the shared memory. The token is transferred the second processor if the first processor is not accessing the shared memory. The second processor accesses the shared memory with the token.

Abstract: A method of processing a stream of audio information received by a multiple processor audio decoder. Processing operations are performed by a first processor on the stream of audio information to produce at set of results. The first processor writes the set of results into a shared memory and a flag is set indicating that the results are ready. In response to the flag, a second processor reads the results from shared memory. When the results have been read from shared memory, the second processor sends a command to the first processor. The first processor then clears the flag.

Abstract: A method of exchanging messages between first and second processors. A pending flag in a first register is polled by the first processor and if the flag is in a first selected logic state, a message is written into a second register with the first processor. The pending flag is set to a second selected logic state with the first processor and an interrupt to the second processor is generated. The message is read from the second register with the second processor when the pending flag is in the second logic state. The pending flag set to the first logic state with the second processor.

Abstract: A method of operating a multiple processor device. A first word of a sequence of words is received in a register. A target processor is determined from the first word and the target processor is interrupted. An input ready bit is set and first word from in the register is read with the target processor. A number of words in the sequence to follow the first word determined from the first word. A word counter is set and the input ready bit is cleared with the target processor. The target processor is returned to main code execution.

Abstract: An audio decoder 100 for operating on a received compressed audio data stream compressed using an algorithm employing transform encoding and a bit allocation routine. A first processor 200 performs a first set of operations on the received compressed audio data stream including parsing the compressed audio data stream, recovering data fields within the compressed audio data stream, calculating a bit allocation, and passing frequency domain coefficients to shared memory. A second digital signal processor 100b performs a second set of operations on data passed from the first digital signal processor to shared memory including performing inverse transform operations on the data passed from the first digital signal processor.

Abstract: A message is transferred from external device through a first processor and from the first processor to a second processor. A check is made that the message passed to the second processor without error. The message is interpreted by a selected one of the first and second processors. Boot operations are performed by the selected processor in response to the interpretation of the message.

Abstract: A method of generating zero detect flag at the output of an adder adding a first vector and a second vector to generate a third vector. A fourth vector is generated from the third vector a carry propagation vector and a carry generation vector. A fifth vector generated using an incremented third vector and an incremented carry propagation vector. A sixth vector generated from the fourth vector and the fifth vector. The bits of the sixth vector bitwise added to obtain the zero detection flag.

Abstract: A voltage controlled oscillator with bias current calibration includes a voltage controlled oscillator 1504. A tuning current source 1510 is coupled to oscillator 1504 in parallel with bias current source 1512 for providing a tuning current to oscillator 1504. A selected control voltage is provided by oscillator 1504 for setting an oscillator output frequency. Control circuitry 1513, 1514 allows adjusting of the tuning current source to optimize bias current.

Abstract: A processing system 100 is provided which includes a memory 107 and memory control circuitry 203. Packing circuitry 215 is operable to receive a stream of video data words in a first YUV format and convert those video data words into a plurality of packed words in a second YUV format. Memory control circuitry 203 is operable to simultaneously store the plurality of packed YUV words in memory 107 in the second format along with a plurality of RGB words.

Abstract: Programmable circuitry (10) is provided including a plurality of logic modules (12) each having at least one input conductor (16). A nearest neighbor conductor (36) is fusibly coupled to output circuitry (25) of a selected logic module (12), the nearest neighbor conductor (36) intersecting the input conductor (16) of a nearest neighbor logic module (12). A fuse (40) disposed at the intersection of the nearest neighbor conductor (36) and the input conductor (16) of the nearest neighbor logic module (12) is provided for selectively establishing electrical coupling therebetween.

Abstract: An apparatus and method for processing a real input signal representing frames of video information is disclosed. The apparatus and method are embodied in a digital filter comprising means for filtering a real input signal to produce therefrom a real output signal having desired characteristics, the filtering means selecting and acting in accordance with ones of a series of single filter operating parameters selected as a function of real input signal conditions and means for recalling the selected ones of the parameters from a memory, the parameters mathematically derived by simulating a plurality of virtual input signals and filtering the virtual input signals through multiple virtual filters to produce virtual desired output signals.

Abstract: A TTL gate (26) with a Darlington output (14,14A,16) includes three circuits (28,30,32) to decrease the gate switching time during an output transition from a high to a low logic state and from a high impedance state to a low logic state. Each speedup circuit drives the gate input transistor (12) for a different length of time, ensuring that the lower output transistor (16) turns on rapidly and remains on until the output transition is complete. The circuits ensure, however, that the additional drive current (82) is time limited to avoid excessive power consumption.

Abstract: A test circuit (10) is connected to a package pin of an integrated circuit via the first node (16). By setting the voltage on the package pin to a sufficient voltage, the test circuit becomes operable to measure DC characteristics of devices in the test circuit. The DC characteristics of the test circuit devices, such as resistors (26 and 34), diodes (44) and transistors (30 and 32) are used to estimate the AC characteristics of the actual integrated circuit. The AC characteristic estimations may be used to screen parts into various speed classes.

Abstract: A floating point processor (10) is provided having a multiplier (48) and an ALU (54) for performing arithmetic calculations simultaneously. The output of the multiplier (48) and ALU (54) are stored in a product register (64) and a sum register (66), respectively. Multiplexers (40,42,44,46) are provided at the inputs to the multiplier (48) and the ALU (54). The multiplexers choose between data in input registers (32,34), product and sum registers (64,66), and an output register (76). Since the multiplier (48) and ALU (54) operate simultaneously, and since the outputs of the multiplier (48) and ALU (54) are available to the multiplexers (40-46), product of sums calculations and sum of products calculations may be performed rapidly. An input stage (12) uses a temporary register (18) to store data from a data bus on the first clock edge, and configuration logic (28) for directing data from the data bus and the temporary register (18) to the input registers (32,34) on a second clock edge.

Abstract: A test circuit (10) is connected to a package pin of an integrated circuit via the first node (16). By setting the voltage on the package pin to a sufficient voltage, the test circuit becomes operable to measure DC characteristics of devices in the test circuit. The DC characteristics of the test circuit devices, such as resistors (26 and 34), diodes (44) and transistors (30 and 32) are used to estimate the AC characteristics of the actual integrated circuit. The AC characteristic estimations may be used to screen parts into various speed classes.

Abstract: An integrated circuit (42) is formed in a semiconductor layer (50) having a defined area. Functional circuitry (12) is formed in semiconductor layer (50) to occupy only a portion of the defined area of semiconductor layer (50), and thus defining an unoccupied area of semiconductor layer (50). A capacitor is formed in semiconductor layer in a substantial portion of the unoccupied area.

Abstract: A register file for a bit slice ALU includes a static RAM array (86) which is addressable by two input read addresses. The addresses decoded by decoders (104) and (106) for input to the array (86). The array (86) simultaneously outputs two data words in response to two read addresses to sense amps (94) and (98). Data can be written into the memory by storing it in a data latch (100) and addressing it with a separate write address. The separate write address is latched in a write address (108) which is enabled on the rising clock edge by control circuit (114).

Abstract: A memory device (10) includes switching circuitry 22 comprising sensing and control circuits (24 and 26) to predict the next state of the output of memory device (12) and to turn on and off current sources (20) responsive to said memory output to provide faster output transitions.

Abstract: A multiplying circuit (10) receives a multiplicand A and multiplies it by multiplier B. An Octal recoder (18) recodes the multiplier B into octal digits having a value from 4 to -4. A tripling generator determines the product of three times the multipicand. Partial product generators (22a-h) connected to the Octal recoder multiplex between the multiplicand A and the 3*A product, and include shifter and inverter circuitry to generate the partial products. Signed digit adders (24a-d, 26a-b and 28) add the partial products.

Abstract: An integrated circuit (10) which includes primary circuit (12) and secondary circuit (17). An enabling circuit (16) allows package pins (15) to be shared between the primary circuit (12) and secondary circuit (17) responsive to voltages on the package pins (15). Enabling circuit (16) further includes disabling circuitry to disable the secondary circuit (17) responsive to a predetermined voltage on the V.sub.cc pin and enables the secondary circuit (17) responsive to a ground voltage on the V.sub.cc pin.