Abstract: A timer circuit provides a wide range of precise and substantially accurate time intervals. The timer circuit includes a ramp generator circuit having a first input for receiving an input signal to start a ramp signal, a second input for receiving a ramp timing control signal, and an output for providing a ramp signal. A comparator has a first input coupled to the output of the ramp generator, a second input coupled to a reference voltage source, and an output for providing an end ramp signal. A counter circuit has a first input for receiving the end ramp signal to begin counting, a second input for receiving a counter timing control signal, and an output for providing a terminal count signal. The end ramp signal and the terminal count signal are combined in an AND gate to provide a signal that is delayed by a predetermined amount from the input signal.

Abstract: A timer circuit provides a wide range of precise and substantially accurate time intervals. The timer circuit includes a ramp generator circuit having a first input for receiving an input signal to start a ramp signal, a second input for receiving a ramp timing conrol signal, and an output for providing a ramp signal. A comparator has a first input coupled to the output of the ramp generator, a second input coupled to a reference voltage source, and an output for providing an end ramp signal. A counter circuit has a first input for receiving the end ramp signal to begin counting, a second input for receiving a counter timing control signal, and an output for providing a terminal count signal. The end ramp signal and the terminal count signal are combined in an AND gate to provide a signal that is delayed by a predetermined amount from the input signal.

Abstract: The present invention is a method and an electrical circuit (28 and 50) for effectively eliminating the effects of time jitter caused by metastable states by rejecting measurements made under timing conditions that could lead to the development of metastable states. In a preferred embodiment, the circuit of the invention effectively eliminates time jitter caused by metastable states in digital oscilloscope circuitry by determining in advance the timing conditions that can lead to such jitter and detecting whenever the transitions of trigger and trigger hold-off signals meet such timing conditions. The circuit then generates a "possible metastable" signal that can be used by the oscilloscope circuitry, or by the controlling software, to reject any measurement made under those timing conditions.

Abstract: A trigger circuit (20, 50, 80, 90, 100) suitable for triggering an oscilloscope on the occurrence of a limited amplitude input signal includes a first comparator (38) for comparing an input signal to a first, low threshold voltage and for generating a first logic signal, and a second comparator (40) for comparing the input signal to a second, high threshold voltage and for generating a second logic signal. The first and second logic signals are combined in a flip-flop circuit (25) to provided an output logic signal such that the output signal changes logic state subsequent to the input signal crossing and recrossing the first, low threshold voltage without crossing the second, high threshold voltage.

Abstract: A triggering control circuit varies a holdoff period for one sweep cycle whereby to lock triggering to a different, selected event viewable on an oscilloscope.