Abstract: An image processing system provides a method for processing an image including classifying the image, comparing the image to stored images, storing the image if the image does not match one of the stored images, and storing a link to a stored image if the image matches one of the stored images.

Abstract: A method for correlating semiconductor process data analyzes a semiconductor device that has been treated by a process, to produce process data related to the process. The data is converted into an image pattern, and automatic image retrieval is used to identify other devices having similar images. The process data is then correlated with prior process data of the other devices having the similar images.

Abstract: A method and structure is provided for an integrated circuit with a semiconductor substrate having an opening provided therein. A doped high conductivity region is formed from doped material in the opening and a diffused dopant region proximate the doped material in the opening. A structure is over the doped high conductivity region selected from a group consisting of a wordline, a gate, a dielectric layer, and a combination thereof.

Abstract: A method for analyzing a semiconductor device tests a semiconductor device to produce first and second data. A clustering method is applied to the first data, creating a clustered first data. The clustered first data is then correlated with the second data to determine analyzed data.

Abstract: A system for presenting tester information is provided, including providing test data of a first parameter and generating a first type of visualization of the first parameter and presenting the first type of visualization of the first parameter. The system includes generating a second type of visualization of the first parameter in response to the presenting of the first type of visualization of the first parameter and presenting the second type of visualization of the first parameter.

Abstract: A system and method for wafer level global bitmap characterization include determining chip level defect data bitmaps from a semiconductor wafer, and consolidating the chip level defect data bitmaps into a global wafer level bitmap that characterizes substantially the entire wafer failure configuration. The global wafer level bitmap is then analyzed and compared with other global wafer level bitmaps to develop correlations thereamong and develop global wafer level bitmap definitions for conducting at least one of wafer-to-wafer, boat-to-boat, and lot-to-lot process analysis based upon the global wafer level bitmap definitions.

Abstract: A method for determination of tunnel oxide weakness is provided. A tunnel oxide layer is formed on a semiconductor wafer. At least one poly gate is formed on the tunnel oxide layer in a flash memory region of the semiconductor wafer. At least one poly island, which is substantially larger than the poly gate, is formed on the tunnel oxide layer in a voltage contrast cell region of the semiconductor wafer. The poly island and the tunnel oxide layer therebeneath form a voltage contrast tunnel oxide cell. A voltage contrast measurement is performed on the voltage contrast tunnel oxide cell. The voltage contrast measurement is then compared with prior such voltage contrast measurements on other such voltage contrast tunnel oxide cells. The tunnel oxide weakness of the tunnel oxide layer is then determined from the voltage contrast measurement comparisons.

Abstract: A method and system of processing tester information of a system under test is provided. Data of a tested characteristic of the system under test is generated. A distribution curve is extracted from the data. A signature of the distribution curve is determined, and a map of the signature on a depiction of the system under test is presented. The distribution curve also can be categorized in a plurality of bins, and bitmaps are generated for the sections in each of the plurality of bins. Systematic signatures are determined from the bitmaps in the block, and the signatures are correlated with the locations on the system under test.

Abstract: A method of testing an integrated circuit is provided, which includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate and a first channel is formed in the first dielectric layer in contact with the semiconductor device. A first contact pad mask layer is formed and a first contact pad in the first contact pad mask layer is formed in contact with the first channel. The first contact pad is used to test the first channel and the semiconductor device and the first contact pad mask layer and the first contact pad are removed.

Abstract: A system of testing wafer process-splits in a semiconductor wafer is provided. A first test is performed on a semiconductor wafer in a plurality of locations to obtain first data. The first data is clustered into a plurality of bins to obtain process-split locations. Second tests are performed on the semiconductor wafer in the process-split locations to obtain second data. The first data and second data arc correlated to determine process-split data.

Abstract: A system for processing tester information is provided. Data is collected for a plurality of dies on a semiconductor wafer. Data and a pattern covering the semiconductor wafer are selected. Selected data are graphed in a trellis of graphs spread across the semiconductor wafer. The trellis of graphs is oriented over an outline of the semiconductor wafer.

Abstract: A method of manufacturing an integrated circuit is provided having a semiconductor wafer. A chemical-mechanical polishing stop layer is deposited on the semiconductor wafer and a first photoresist layer is processed over the chemical-mechanical polishing stop layer. The chemical-mechanical polishing stop layer and the semiconductor wafer are patterned to form a shallow trench and a shallow trench isolation material is deposited on the chemical-mechanical polishing stop layer and in the shallow trench. A second photoresist layer is processed over the shallow trench isolation material leaving the shallow trench uncovered. The uncovered shallow trench is then treated to become a chemical-mechanical polishing stop area. The shallow trench isolation material is then chemical-mechanical polished to be co-planar with the chemical-mechanical stop layer and the chemical-mechanical polishing stop treated area.

Abstract: A method for processing tester information is provided. The number of clusters of data in the tester information is determined to determine the number of data clusters. A basis is determined from the tester information to be used for plotting the data clusters. The data clusters are plotted on a plurality of trellis charts to form a trellising plot with a trellis of trellis charts.

Abstract: A method for processing tester information is provided. The number of clusters of data in the tester information is determined to determine the number of data clusters. A basis is determined from the tester information to be used for plotting the data clusters. The data clusters are plotted on a plurality of trellis charts to form a trellising plot with a trellis of trellis charts.

Abstract: A method is provided for manufacturing a MirrorBit® Flash memory with high conductivity bitlines and shallow trench isolation integration. A hard mask is formed over a substrate and used to form a core trench and a shallow trench isolation (STI) trench. The trenches are filled with an insulating material in an STI fill process. A core mask is formed over the STI trenches and exposing the core trenches. The insulating material is removed from the core trenches and the core and hard mask are removed. A doped bitline material is deposited on the surface of the semiconductor, which fills the core trench. The surface of the semiconductor is planarized, inlaying insulating material and doped bitline material in the trenches. A thermal anneal causes the dopant diffusion from the doped bitline material into the substrate to form the high conductivity bitlines.

Abstract: Spacers are formed on a semiconductor device by depositing a spacer layer on the semiconductor device. The semiconductor device is subjected to an anisotropic etching process to leave at least a portion of the spacer layer covering the semiconductor device. The semiconductor device is then subjected to an isotropic etching process to form the spacers on the semiconductor device.