Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for reporting a synchronization indication and for applying a synchronization window. As an example, a system is discussed that includes: a head assembly including a first read head and a second read head; a down track distance calculation circuit operable to calculate a down track distance between the first read head and the second read head; and a synchronization mark detection circuit. The synchronization mark detection circuit is operable to: assert a synchronization mark window based at a location based at least in part on the down track distance; query a first data set derived from the first read head for a synchronization mark occurring within the synchronization mark window; and query a second data set derived from the second read head for the synchronization mark occurring within the synchronization mark window.

Abstract: An apparatus for storing data includes a storage medium with user data regions and with servo data regions containing preamble patterns. Servo data in the servo data regions is written with a varying clock frequency across the storage medium. The apparatus also includes a head assembly disposed in relation to the storage medium and operable to read and write data on the storage medium. The apparatus also includes a preamble detection circuit adapted to search an input stream derived from the head assembly for the preamble patterns in a number of frequency bins.

Abstract: Various embodiments of the present invention provide systems and methods for determining changes in fly-height. For example, various embodiments of the present invention provide storage devices that include a storage medium having servo data thereon. A read/write head assembly is disposed in relation to the storage medium. A servo based fly-height adjustment circuit receives the servo data via the read/write head assembly, and calculates a first harmonics ratio based on the received data and compares the first harmonics ratio with a second harmonics ratio to determine an error in the distance between the read/write head assembly and the storage medium.

Abstract: Various embodiments of the present invention provide systems and methods for low overhead disk wobble compensation. As an example, a method for performing synchronous wobble compensation processing is disclosed. The method includes providing a medium that includes a servo data region and a user data region. The servo data region includes a clock recovery pattern and a location pattern. A detectable pattern is written to the user data region a known number of bit periods from the location pattern. The detectable pattern is read back, and a fractional processing delay is calculated. Based at least on the fractional processing delay and a known number of bit periods from the location pattern to the end of the servo data region, a wobble compensation pattern is written an integral number of bit periods from the location pattern.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for processing servo data using two or more sensing heads.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for reporting a synchronization indication and for applying a synchronization window. As an example, a system is discussed that includes: a head assembly including a first read head and a second read head; a down track distance calculation circuit operable to calculate a down track distance between the first read head and the second read head; and a synchronization mark detection circuit. The synchronization mark detection circuit is operable to: assert a synchronization mark window based at a location based at least in part on the down track distance; query a first data set derived from the first read head for a synchronization mark occurring within the synchronization mark window; and query a second data set derived from the second read head for the synchronization mark occurring within the synchronization mark window.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for processing servo data using two or more sensing heads.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.

Abstract: A method and system for performing a shortened acquire cycle for at least one fragment of at least one data sector having coherently written fragments, the coherently written fragments being written during a single rotation of a storage medium. The method includes performing a full acquire cycle for a first fragment of a particular data sector of the at least one data sector. The method further includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. The method also includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. Additionally, the method includes performing the shortened acquire cycle for the at least one subsequent coherently written fragment.

Abstract: A system and method for power management in a hard disk drive (HDD) assembly incorporating two or more read sensors includes directing a read/write head to follow a track; depowering one or more read sensors and readpath circuits associated with the read sensors; reading an analog readback signal through the first read sensor; processing the signal through an analog front-end to generate an input signal; sampling the input signal through an analog to digital converter at a first frequency to generate a first sampling signal; sampling the input signal through a second analog to digital converter at a second frequency to generate a second sampling signal; and generating a digital output signal from either or both sampling signals at a third sampling frequency through a digital signal processor. The method may additionally comprise adjusting a sampling frequency when power level reaches a threshold.

Abstract: A servo system includes a first equalizer circuit operable to filter digital servo data samples derived from a first read head to yield first equalized data, a second equalizer circuit operable to filter digital servo data samples derived from a second read head to yield second equalized data, a first interpolator operable to interpolate the first equalized data to yield a number of first interpolated outputs at different phases, a second interpolator operable to interpolate the second equalized data to yield a number of second interpolated outputs at different phases, and a phase tracking and signal combining circuit operable to select and combine most closely aligned signals from the first interpolated outputs and the second interpolated outputs to yield a combined servo data signal.

Abstract: A method and system for performing a shortened acquire cycle for at least one fragment of at least one data sector having coherently written fragments, the coherently written fragments being written during a single rotation of a storage medium. The method includes performing a full acquire cycle for a first fragment of a particular data sector of the at least one data sector. The method further includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. The method also includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. Additionally, the method includes performing the shortened acquire cycle for the at least one subsequent coherently written fragment.

Abstract: A servo system includes multiple interpolators operable to interpolate equalized data for multiple signal paths in a two dimensional magnetic recording system to yield interpolated signals at different phases, scaling circuits operable to scale the interpolated signals by adaptive scaling factors, a signal combining circuit operable to combine the scaled signals, a phase tracking circuit operable to select one of the phases of the combined signal, and an error gradient circuit operable to adapt the adaptive scaling factors.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide clock generation systems that include: a first clock multiplier circuit, a second clock multiplier circuit, a modulus accumulator circuit, and a data clock phase control circuit. The first clock multiplier circuit is operable to multiply a reference clock by a first multiplier to yield a first domain clock, and the second clock multiplier circuit is operable to multiply the reference clock by a second multiplier to yield a second domain clock. The modulus accumulator circuit is operable to yield a value indicating a fractional amount of the second domain clock that an edge of the second domain clock is offset from a trigger signal. The data clock phase control circuit is operable to phase shift the second domain clock by a phase amount corresponding to the fractional amount.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head and to control positioning of the read/write head relative to the storage disk. The control circuitry comprises an inter-track interference detector configured to process a signal read from at least a given track of the storage disk via the read/write head in order to detect interference in that signal from at least one other track of the storage disk. The control circuitry further comprises an inter-track interference based head position controller configured to adjust the positioning of the read/write head responsive to the detected interference.

Abstract: A contact event between a sensing device and a storage medium is detected by receiving a signal indicating a physical proximity between the sensing device and the storage medium; generating a plurality of frequency bin outputs; comparing one or more frequency bin outputs to a corresponding first level threshold to yield a corresponding comparator output; summing the comparator output with at least one prior instance of the comparator output to yield an aggregated value; comparing the aggregated value to an aggregate threshold to yield an aggregate output; and generating a contact event output if one or more of a first group of the plurality of frequency bin outputs has an associated aggregate output set to a predefined binary value and a predefined minimum number of a second group of the plurality of frequency bin outputs has an associated aggregate output set to a predefined binary value.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head. The control circuitry comprises clock adjustment circuitry configured to generate a control signal for adjusting a parameter of a clock signal based at least in part on timing information obtained by detecting a timing pattern on a surface of the storage disk. The control signal is generated utilizing at least a predictive correction control loop, with the clock adjustment circuitry comprising predictive control firmware that implements at least a portion of the predictive correction control loop.

Abstract: Methods and apparatus are provided for validating a detection of RRO address marks. After a potential RRO address mark is detected, a disclosed RROAM validation metric evaluates the energy of the remaining RRO data bits in the servo sector, relative to a predefined energy threshold. In addition, the number of remaining RRO data bits in the servo sector is compared to an expected value. The detected RRO address mark is validated in an exemplary embodiment if the RROAM validation metric satisfies the predefined energy threshold and the proper number of remaining RRO data bits is detected in the servo sector. The potential RRO address mark can optionally be discarded if the potential RRO address mark is not validated.

Abstract: A clock phase measurement circuit comprises a selector circuit operable to inject one of a first analog clock signal or a second analog clock signal into a signal path configured to carry an analog data signal, so that the injected analog clock signal replaces the data signal. An Analog to Digital Converter (ADC) converts the injected analog clock signal to a digital clock signal. A counter selects a time, using the second analog clock signal, to determine at least one of a phase or a magnitude of the digital clock signal. A measurement circuit determines at least one of the phase or the magnitude of the digital clock signal for at least one frequency at the selected time.