Abstract: A self-setting/resetting latch circuit is disclosed that includes resistive loads for inverters used for setting and clearing the latch. In a first embodiment, the resistive loads cause the latch circuit to automatically set in response to a power supply voltage going low. In an alternate embodiment, the latch circuit is configured to be self-resetting or self-clearing when the power supply voltage goes low by reversing the set and clear terminals of the latch circuit and selecting a different node to be the output terminal of the latch circuit. The disclosed latch circuit is small and robust and draws zero power in the set state.

Abstract: A self-setting/resetting latch circuit is disclosed that includes resistive loads for inverters used for setting and clearing the latch. In a first embodiment, the resistive loads cause the latch circuit to automatically set in response to a power supply voltage going low. In an alternate embodiment, the latch circuit is configured to be self-resetting or self-clearing when the power supply voltage goes low by reversing the set and clear terminals of the latch circuit and selecting a different node to be the output terminal of the latch circuit. The disclosed latch circuit is small and robust and draws zero power in the set state.

Abstract: Systems and techniques for single-wire communications are described. A described technique includes detecting transitions on a single-wire bus that are produced by a host device, determining an estimated baud rate of the host device based on the transition, and communicating with the host device based on the estimated baud rate. Determining the estimated baud rate can include charging a capacitor based on a charging rate in response to a detection of a first transition of the transitions, sampling a capacitor voltage associated with the capacitor in response to a detection of a second transition of the transitions, and adjusting the charging rate based on a comparison between the capacitor voltage and a reference voltage.

Abstract: Systems and techniques for single-wire communications are described. A described technique includes detecting transitions on a single-wire bus that are produced by a host device, determining an estimated baud rate of the host device based on the transition, and communicating with the host device based on the estimated baud rate. Determining the estimated baud rate can include charging a capacitor based on a charging rate in response to a detection of a first transition of the transitions, sampling a capacitor voltage associated with the capacitor in response to a detection of a second transition of the transitions, and adjusting the charging rate based on a comparison between the capacitor voltage and a reference voltage.

Abstract: Systems and techniques for single-wire communications are described. A described technique includes detecting transitions on a single-wire bus that are produced by a host device; determining an estimated baud rate of the host device based on the transitions by approximating a bit transition rate associated with the transitions by iteratively adjusting a charging rate of a capacitor to match the bit transition rate; and communicating with the host device based on the estimated baud rate.

Abstract: Systems and techniques for single-wire communications are described. A described technique includes detecting transitions on a single-wire bus that are produced by a host device; determining an estimated baud rate of the host device based on the transitions by approximating a bit transition rate associated with the transitions by iteratively adjusting a charging rate of a capacitor to match the bit transition rate; and communicating with the host device based on the estimated baud rate.

Abstract: An integrated circuit including operational circuitry operable in response to at least one control signal asserted to an external node from an external source, and test circuitry coupled to the external node and the operational circuitry. In response to data asserted to the external node from an external source, the test circuitry enters a test mode in which it tests, configures, or reconfigures the operational circuitry. The test circuitry also asserts to the operational circuitry each control signal received at the external node (or an amplified or translated version thereof). Other aspects of the invention include test circuitry for use in a circuit having an access node and methods for performing on-chip testing, configuration, and control of operational circuitry within a chip in response to test data and at least one control signal asserted from an external source to an external node.

Abstract: A switched capacitor array circuit for use in a voltage regulator, including L, M and N banks of capacitor positions disposed intermediate an input node and a ground node, between the input and output nodes and between the output node and the ground node, respectively. Switching circuitry operates to switch three capacitors between a common phase configuration and a gain phase configuration. Two of the capacitors are disposed in one of the L, M and N banks of capacitor positions, with the third capacitor being disposed in a different one of the L, M and N banks of capacitor positions in the common phase configuration. When switched from the common phase to the gain phase configuration, at least one of the three capacitors is moved to a different capacitor position.

Abstract: A system and method for providing for on-chip configuration, control and testing of mixed signal circuitry within an integrated circuit. A dual signal interface conveys the serial data and clock signals used for controlling the enablement, disablement and operational modes of the synchronous circuitry responsible for such on-chip configuration, control and testing, thereby minimizing the amount of overhead, in terms of interface terminals needed, for providing such capability.

Abstract: A multiple over current protection circuit for regulating current through an analog switch coupled between a power supply and a load. In a first circuit, a comparator monitors a voltage drop across the analog switch. When the voltage drop exceeds a reference voltage, the comparator momentarily activates a first transistor and causes an amplifier to enter a current limiting mode. The activated first transistor causes the analog switch to momentarily turn off. In a second circuit, the comparator activates a second transistor. During the current limiting mode of the amplifier, a constant voltage is maintained at the source of the second transistor and the load side of the analog switch. A current source draws a current through the second transistor. Also, the current flowing through the analog switch tracks the current flowing through the second transistor.

Abstract: A method and apparatus are directed to emulating an emitter follower with a small PNP transistor that is arranged in a PNP multiplier configuration. The PNP multiplier includes a PNP emitter follower and a current mirror. The PNP follower is coupled between the input and the output. A current mirror is coupled to the collector of the PNP follower such that mirror produces a current that is a scaled version of the collector current from the PNP follower. The current mirror is arranged to scale the PNP collector current by a factor of N. The effective output current from the PNP multiplier circuit corresponds to &bgr;·IIN·(N+1), where &bgr; corresponds to the large signal forward gain of the PNP follower. By multiplying the output current by a scaling factor, the effective forward gain of the PNP transistor is increased while utilizing a small geometry PNP device.

Abstract: A capacitor array circuit having at least two capacitors, switching circuitry coupled to the capacitors and to input, output and common nodes and control circuitry. The control circuitry operates to sequentially switch the array through three different states so that a voltage is developed across each of the capacitors which is at a fixed value proportional to a voltage present at the input node. The fixed and thus determinate voltage drop across each of the capacitors operates to define voltages at any nodes intermediate the capacitors thereby, among other things, insuring reliable operation of the capacitor array circuit.

Abstract: A band gap circuit that may be implemented in a standard CMOS process including a pair of parasitic vertical PNP transistors operating at a different current density. The PNP transistors have common collectors and common bases and produce a difference in base-emitter voltages which is developed across a resistor so as to produce a current having a positive temperature coefficient. The current is used to produce a positive temperature coefficient voltage which is combined with another voltage having a negative temperature coefficient to produce a band gap reference voltage. A bias voltage is applied between the base and collector of each of the PNP transistors, typically on the order of 500 millivolts. This causes the emitters of the PNP transistors to be at a voltage which can be sensed by an error amplifier implemented with standard N type MOS input transistors while maintaining a capability of operating using a relatively low power supply voltage.

Abstract: A linear regulator includes an amplifier that provides a control signal in response to a comparison between a feedback signal and an output signal. A pass element in the regulator selectively couples power from an unregulated power signal to an output node in response to the control signal. A compensation circuit that includes negative gain is arranged to provide the feedback signal in response to an output signal at the output node. In one example, the compensation circuit includes an inverting amplifier that provides an intermediary signal in response to the output signal, and the intermediary signal is coupled to a feedback network that provides the feedback signal. In another example, the compensation circuit includes an inverting amplifier that cooperates with a feedback network to provide the feedback signal. The closed-loop transfer functions of the compensation circuits provide a feed-forward zero that enables stable operation of the LDO regulator.

Abstract: A switched capacitor array circuit and method, with the array circuit being coupled between an input node and an output node and which is capable of providing multiple gain states. The array circuit includes an L band of capacitor positions disposed between the input node and a third node, typically the circuit common, an M bank of capacitor positions coupled between the input and output nodes and an N bank of capacitor positions coupled between the output node and the third node. Each of the L, M and N banks of capacitor positions includes series and parallel capacitor positions. In one embodiment, the array includes first, second and third capacitors together with switching circuitry and control circuitry. The control circuitry causes the switching circuitry to switch the array circuit between a common phase configuration and a gain phase configuration so as to provide a gain state value Gsc.

Abstract: A switched capacitor circuit, for use in voltage converters and the like, which includes a switched capacitor array, a plurality of MOS transistor switches and drive circuitry for controlling the state of the switches. The drive circuitry alternates between a first phase where at least one capacitor of the array is connected by the switches between an input node and an output node and a second phase where the capacitor is connected in series between one of the output and input nodes and a third node, such as a circuit common. Boost and buck gain configurations are achieved when connected to the output and input nodes, respectively. A voltage management feature is implemented to control voltages produced in the array so that no PN junction of the transistor switches formed by a body and the drain/source regions disposed in the body becomes forward biased.

Abstract: A current sensing circuit which provides for accurate in-line current sensing with extremely low insertion loss. A low valued resistor (e.g., 0.005 ohms) is connected in series with the source and load of the current to be measured. An analog-to-digital converter (ADC) is used to measure the resulting voltage generated across the resistor. In order to minimize inaccuracies due to voltage offsets introduced by the measurement circuitry when measuring the low voltages generated across such a low resistance, the ADC is "chopped," thereby causing self cancellation of any such offset voltages. A voltage source which provides a reference voltage for the ADC has a temperature coefficient which is approximately equal in magnitude to the temperature coefficient of the resistor. Hence, for a given current through the resistor, the reported voltage as measured across the resistor remains constant over temperature.

Abstract: Overvoltage protection circuit (10) has a power transistor (11) that drives an inductive load (19). A resistor (16) is connected between an output electrode (14) of the transistor and a control electrode (12) of the transistor, and a constant current source (18) is also connected to the control electrode. The resistor and constant current source determine an effective zener voltage to limit the maximum voltage which can exist at the transistor output electrode (14), and this is accomplished without the use of a zener diode while utilizing a minimum number of components. This effective zener diode voltage can be readily adjusted by adjusting either the magnitude of the resistor (16) or the constant current source (18).

Abstract: A transistor sense electrode (20) is coupled to the input branch (24) of a current mirror (22). The current mirror's branch (26) carries a current substantially equal to the current in the input branch to indicate the current flowing in the transistor. A preferred embodiment includes an amplifier (30) which senses the difference between the voltage at the sense electrode (20) and a reference voltage (Vx). The sensed difference in voltage causes the amplifier to apply a control signal to the current mirror to vary the current in the input branch so as to hold the sense electrode's voltage at the level of the reference voltage (Vx). A preferred package for the system's circuitry is also disclosed.

Abstract: A method and apparatus is disclosed for measuring and/or controlling the level of current in a Sense FET which includes a power transistor (M1) and a sense transistor (M2). The transistors (M1) and (M2) are both biased to operate in a linear mode, and the Vds of the sense transistor (M2) is compared to a predetermined fraction of the Vds of the power transistor (M1). A control signal is generated that is representative of the results of the comparison, and, in one embodiment, that control signal is used in a feedback arrangement to drive the Vds of the sense transistor (M2) to the predetermined fraction of the Vds of the power transistor (M1). Consequently, the level of current carried by the sense transistor (M2) is caused to be equal to the same predetermined fraction of the current carried by the power transistor (M1).